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september 2013 doc id 17639 rev 4 1/102 1 L99PM62GXP power management ic with lin and high speed can features two 5v voltage regulators for microcontroller and peripheral supply no electrolytic capacitor required on regulator outputs ultra low quiescent current in standby modes programmable reset generator for power-on and undervoltage configurable window watchdog and fail safe output lin 2.1 compliant (saej2602 compatible) transceiver advanced hs can transceiver (iso 11898-2/- 5 and sae j2284 compliant) with local failure and bus failure diagnosis hs can transceiver supports partial networking complete 3-channel contact monitoring interface with programmable cyclic sense functionality programmable periodic system wake-up feature st spi interface for mode control and diagnosis 5 fully protected high-side drivers with internal 4-channel pwm generator 2 low-side drivers with active zener clamping 4 internal pwm timers 2 operational amplifiers with rail-to-rail outputs (v s ) and low voltage inputs temperature warning and thermal shutdown applications automotive ecu's such as door zone and body control modules description the L99PM62GXP is a power management system ic that provides electronic control units with enhanced system power supply functionality, including various standby modes, as well as lin and hs can physical communication layers. the device?s two low-drop voltage regulators supply the system microcontroller and external peripheral loads such as sensors and provide enhanced system standby functionality with programmable local and remote wake-up capability. in addition, five high-side drivers, two low-side drivers and two operational amplifiers increase the system integration level. the st standard spi interface (3.0) allows control and diagnosis of the device and enables generic software development. table 1. device summary package order codes tube tape and reel powersso-36 L99PM62GXP L99PM62GXPtr powersso-36 www.st.com
contents L99PM62GXP 2/102 doc id 17639 rev 4 contents 1 block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 voltage regulator: v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.2 voltage regulator: v 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 increased output current capability for voltage regulator v 2 . . . . . . . . . 13 2.1.4 voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.5 voltage regulator behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 v1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.4 vbat standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.6 wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.7 cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.8 timer interrupt / wake-up of microcontroller by timer . . . . . . . . . . . . . . . 19 2.3 functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.1 change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5.1 single failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5.2 multiple failures ? entering forced v bat standby mode . . . . . . . . . . . . . 27 2.6 reset output (nreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.7 operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.8 lin bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.8.1 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.8.2 wake up (from lin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.8.3 lin pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.9 high speed can bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.9.1 can error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.9.2 wake up (from can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L99PM62GXP contents doc id 17639 rev 4 3/102 2.9.3 can sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.9.4 can receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.9.5 can looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.10 serial peripheral interface (st spi standard) . . . . . . . . . . . . . . . . . . . . . . 33 3 protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1 power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.1 v s overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1.2 vs undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 37 3.3 high-side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4 low-side driver outputs rel1, rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5 spi diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.1 supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.3 power-on reset (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.4 voltage regulator v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.5.5 voltage regulator v 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.5.6 reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.7 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.8 high-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.5.9 relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.5.10 wake up inputs (wu1... wu3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5.11 high speed can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5.12 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.5.13 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
contents L99PM62GXP 4/102 doc id 17639 rev 4 5.5.14 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.5.15 inputs txd_c and txd_l for flash mode . . . . . . . . . . . . . . . . . . . . . . 65 6 st spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1.2 operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1.3 global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.1.5 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.6 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.1.7 format of data shifted out at sdo during write cycle . . . . . . . . . . . . . . 73 6.1.8 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.1.9 format of data shifted out at sdo during read cycle . . . . . . . . . . . . . . . 75 6.1.10 read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.11 read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2.3 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2 powersso-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
L99PM62GXP list of tables doc id 17639 rev 4 5/102 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. wake up sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 6. persisting fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. pwm configuration for high-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 8. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 10. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 12. thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 13. supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 14. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 15. power-on reset (vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 16. voltage regulator v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 17. voltage regulator v 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 18. reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 19. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 20. output (out_hs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 21. outputs (out1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 22. relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 23. wake up inputs (wu1... wu3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 24. can communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 25. can transmit data input: pin txdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 26. can receive data output: pin rxdc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 table 27. can bus common mode stabilization output termination: pin split . . . . . . . . . . . . . . . . . 56 table 28. can transmitter and receiver: pins canh and canl . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 29. can transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 30. lin transmit data input: pin txd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 31. lin receive data output: pin rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 32. lin transmitter and receiver: pin lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 33. lin transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 34. lin pull-up: pin linpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 35. operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 36. input: csn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 37. input clk, di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 38. di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 39. do output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 40. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 41. csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 42. rxdl/nint timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 43. inputs txd_c and txd_l for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 44. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 45. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 46. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 47. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 48. address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
list of tables L99PM62GXP 6/102 doc id 17639 rev 4 table 49. write command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 50. write command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 51. write command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 52. format of data shifted out at sdo during write cycle: global status register . . . . . . . . . . . 73 table 53. format of data shifted out at sdo during write cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 73 table 54. format of data shifted out at sdo during write cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 73 table 55. read command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 56. read command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 57. read command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 58. format of data shifted out at sdo during read cycle: global status register. . . . . . . . . . . . 75 table 59. format of data shifted out at sdo during read cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 75 table 60. format of data shifted out at sdo during read cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 75 table 61. read and clear status command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 62. read and clear status command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 63. read and clear status command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 64. format of data shifted out at sdo during read and clear status: global status register . . . 76 table 65. format of data shifted out at sdo during read and clear status: data byte 1. . . . . . . . . . . 76 table 66. format of data shifted out at sdo during read and clear status: data byte 2. . . . . . . . . . . 77 table 67. read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 68. id-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 69. family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 70. silicon version identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 71. spi-frame-id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 72. spi register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 73. spi register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 74. spi register: ctrl register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 75. spi register: stat register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 76. overview of control registers data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 77. control register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 78. control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 79. control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 80. control register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 81. control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 82. control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 83. control register 3: command data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 84. control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 85. control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 86. control register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 87. control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 88. control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 89. control register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 90. control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 91. control register 5, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 92. control register 6: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 93. control register 6, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 94. control register 6, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 95. overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 96. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 97. status register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 98. status register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 99. status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 100. status register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
L99PM62GXP list of tables doc id 17639 rev 4 7/102 table 101. status register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 102. status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 103. status register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 104. status register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 105. status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 106. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 table 107. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
list of figures L99PM62GXP 8/102 doc id 17639 rev 4 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. voltage source with external pnp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. voltage source with external pnp and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. voltage source with external npn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. voltage source with external npn and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. watchdog in flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. change watchdog timing within long open window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. change watchdog timing within window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. general procedure to change watchdog timing out of fail safe mode. . . . . . . . . . . . . . . . . 25 figure 15. change watchdog timing out of fail safe mode (watchdog failure) . . . . . . . . . . . . . . . . . . . 25 figure 16. example: exit fail safe mode from watchdog failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. lin master node configuration using lin_pu (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. can wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. over voltage and under voltage protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21. phase shifted pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23. thermal data of powersso-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 24. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 25. powersso-36 thermal resistance junction to ambient vs pcb copper area (v1 on) . . . 46 figure 26. powersso-36 thermal impedance junction to ambient vs pcb copper area (single pulse with v1 on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 27. powersso-36 thermal fitting model (v1 on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 28. watchdog timing (long, early, late and safe window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 29. watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 30. lin transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 31. spi ? transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 32. spi - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 33. spi output timing (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 34. spi output timing (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 35. spi ? csn low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 68 figure 36. read configuration register (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 37. write configuration register (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 38. format of data shifted out at sdo during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 39. format of data shifted out at sdo during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 40. format of data shifted out at sdo during read and clear status operation . . . . . . . . . . . . 77 figure 41. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
L99PM62GXP block diagram and pin descriptions doc id 17639 rev 4 9/102 1 block diagram and pin descriptions figure 1. block diagram ', /2*,& :lqgrz :dwfkgrj 9 v $*1' 9 :8 &61 &/. '2 287b+6 287 5(/ 5(/ :8 7hps3uhzduqlqj 6kxwgrzq 8qghuyrowdjh 2yhuyrowdjh 6kxwgrzq 5['b/1,17 7['b/ 15hvhw 95(* 9p$ 9 287 /,1 /,138 23 23 23brxw 23 23 23brxw +6&$1 ,62 7['b& 5['b& &$1b+ 63/,7 &$1b/ 287)62 3*1' :8 &$16xsso\ 95(* 9p$ 63, 287 /rz6lgh p$ 2xwsxw&odps +ljk6lgh p$ /,1fhuwlilhg /,1 6$(- /rz6lgh p$ 2xwsxw&odps +ljk6lgh p$ +ljk6lgh p$ +ljk6lgh p$ +ljk6lgh p$ 7lphu 7lphu :dnh8s,q :dnh8s,q :dnh8s,q fkdqqho 3:0*hqhudwru $*9
block diagram and pin descriptions L99PM62GXP 10/102 doc id 17639 rev 4 table 2. pin definition pin symbol function 1 agnd analog ground 2 rxdc can receive data output 3 txdc can transmit data input 4 canh can high level voltage i / o 5 canl can low level voltage i / o 6 split can reference voltage output, can termination 7 cansup can supply input; to allow external can supply from v 1 or v 2 regulator. 8 nreset nreset output to micro controller; internal pull-up of typical 100 k (reset state = low) 9v 1 voltage regulator 1 output: 5 v supply e.g. micro controller, can transceiver 10 v 2 voltage regulator 2 output: 5 v supply for external loads (ir receiver, potentiometer, sensors) or can transceiver. v 2 is protected against reverse supply. 11 txdl lin transmit data input 12 rxdl/nint rxdl -> lin receive data output nint -> indicates local/remote wake-up events or provides a programmable timer interrupt signal 13 op2+ non inverting input of operational amplifier 2 14 op2- inverting input of operational amplifier 2 15 op2_out output of operational amplifier 2 16 di spi: serial data input 17 do spi: serial data output 18 clk spi: serial clock input 19 csn spi: chip select not input 20?22 wu1?3 wake-up inputs 1to 3: input pins for static or cyclic monitoring of external contacts 23 op1_out output of operational amplifier 1 24 op1- inverting input of operational amplifier 1 25 op1+ non inverting input of operational amplifier 1 26 out4 high-side driver output (7 , typ) 27 out3/fso configurable as high-side driver output (7 , typ) or fail safe output pin (default) 28 out2 high-side driver output (7 , typ) 29 out1 high-side driver output (7 , typ) 30 out_hs high-side driver (1 , typ) 31 v s power supply voltage 32 linpu high-side driver output to switch off lin master pull up resistor 33 lin lin bus line 34 rel1 low-side driver output (2 typ)
L99PM62GXP block diagram and pin descriptions doc id 17639 rev 4 11/102 figure 2. pin connection (top view) note: it is recommended to connect the pgnd and agnd pins directly to the tab. 35 rel2 low-side driver output (2 typ) 36 pgnd power ground (rel1/2, lin and can gnd), to be externally connected to agnd table 2. pin definition (continued) pin symbol function 5['/1,17 &$1+ '2 &/. 9 287b+6 $*1' 3rzhu662 5['& 7['& 15(6(7 9 7['/ 233 230 23287 ', 63/,7 &$1683 3*1' 9v 5(/ 5(/ 287)62 287 287 233 230 23287 :8 :8 :8 &61 /,138 /,1 287 &$1/ 7$% $*1' $*9
detailed description L99PM62GXP 12/102 doc id 17639 rev 4 2 detailed description 2.1 voltage regulators the L99PM62GXP contains two independent and fully protected low drop voltage regulators, which are designed for very fast transient response and don?t require electrolytic output capacitors for stability. the output voltage is stable with ceramic load capacitors > 220 nf. 2.1.1 voltage regulator: v 1 the v 1 voltage regulator provides 5 v supply voltage and up to 250 ma continuous load current and is mainly intended for supply of the system microcontroller. the v 1 regulator is embedded in the power management and fail-safe functionality of the device and operates according to the selected operating mode. it can be used to supply the internal hs can transceiver via the cansup pin externally. in case of a short circuit condition on the can bus, the output current of the transmitter is limited to 100 ma and the transceiver is turned off in order to ensure continued supply of the microcontroller. in addition the regulator v 1 drives the L99PM62GXP internal 5 v loads. the voltage regulator is protected against overload and overtemperature. an external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. current limitation of the regulator ensures fast charge of external bypass capacitors. the output voltage is stable for ceramic load capacitors > 220 nf. if the device temperature exceeds the tsd1 threshold, all outputs (outx, relx, v 2 , lin) is deactivated except v 1 . hence the micro controller has the possibility for interaction or error logging. in case of exceeding tsd2 threshold (tsd2>tsd1), also v 1 is deactivated (see state chart in chapter 3: protection and diagnosis ). a timer is started and the voltage regulator is deactivated for t tsd = 1sec. during this time, all other wake up sources (can, lin, wu1 to3 and wake up of c by timer) are disabled. after 1 sec, the voltage regulator tries to restart automatically. if the restart fails 7 times, within one minute, without clearing and thermal shutdown condition still exists, the L99PM62GXP enters the forced v bat standby mode. in case of short to gnd at ?v 1 ? after initial turn on (v 1 < 2v for t > t v1short ) the L99PM62GXP enters the forced v bat standby mode. reactivation (wake-up) of the device can be achieved with signals from can, lin, wu1..3 or periodic wake by timer (see section 2.2.8: timer interrupt / wake-up of microcontroller by timer ).
L99PM62GXP detailed description doc id 17639 rev 4 13/102 2.1.2 voltage regulator: v 2 the voltage regulator v 2 can supply additional 5 v loads (e.g. logic components or the integrated hs can transceiver or external loads such as sensors or potentiometers). the maximum continuous load current is 100 ma. the regulator is protected against: overload overtemperature short circuit (short to ground and battery supply voltage) reverse biasing 2.1.3 increased output current capability for voltage regulator v 2 for applications which require high output currents, the output current capability of the regulator can be increased my means of the integrated operational amplifiers and an external pass transistor. figure 3. voltage source with external pnp figure 4. voltage source with external pnp and current limitation figure 3 shows a possible configuration with a pnp pass element using voltage regulator 2 to provide the voltage reference for the regulated output voltage v3. 9 &l & &hp & 9v 9 & /30 5 5 5e 5 5 5 0-'& 23[b287 23[ 23[ $*9 9 &l & &hp & 9v 9 & /30 5 5 5e 5 5 5 0-'& 5 %& 23[b287 23[ 23[ $*9
detailed description L99PM62GXP 14/102 doc id 17639 rev 4 the vs operating range for this circuit is 5.5 v to 18 v. it is important the respect the input common mode range specified for the operational amplifiers. the output voltage v3 can be calculated using the following formula: the circuit in figure 4 provides additional current limitation using an additional pnp transistor and r6 which allows setting the current limit. figure 5. voltage source with external npn figure 6. voltage source with external npn and current limitation figure 5 shows a possible configuration with an npn pass element using voltage regulator 2 to provide the voltage reference for the regulated output voltage v3. this circuit requires fewer components compared to the configuration in figure 3 but has a limited v s operating range (6 v to 18 v). the output voltage v3 can be calculated using the following formula: the circuit in figure 6 provides additional current limitation using an additional npn transistor and r5 which allows setting the current limit. v 3 v 2 2 ----- - r 1 r 2 + r 2 -------------------- - v [] ? = 9 &l & &hp & 9v 9 & /30 5 5 5 0-'& 23[b287 23[ 23[ 5 $*9 9 &l & &hp & 9v 9 & /30 5 5 5 5 5 0-'& %& 23[b287 23[ 23[ $*9 v 3 v 2 2 ----- - r 1 r 2 + r 2 -------------------- - v [] ? =
L99PM62GXP detailed description doc id 17639 rev 4 15/102 alternatively, voltage regulator 1 can be used to provide the 5 v reference for this topology. however, the additional current consumption through r3 and r4 has to be considered in v 1 standby mode. 2.1.4 voltage regulator failure the v 1, and v 2 regulator output voltages are monitored. in case of a drop below the v 1, v 2 ? fail thresholds (v 1,2 < 2 v, typ for t > 2 s), the v 1,2 -fail bits are latched. the fail bits can be cleared by a dedicated spi command. short to ground detection if 4 ms after turn on of the regulator the v 1,2 voltage is below the v 1,2 fail thresholds, (independent for v 1,2 ), the L99PM62GXP identifies a short circuit condition at the related regulator output and the regulator is switched off. in case of v 1 short to gnd failure the device enters v bat standby mode automatically. bits forced v bat std2/shtv 1 and v 1 fail were set. in case of a v 2 short to gnd failure the v 2 short and v 2 fail bit is set. if the output voltage of the corresponding regulator once exceeded the v 1,2 fail thresholds the short to ground detection is disabled. if a short to ground condition occurs the regulator outputs switches off due to thermal shutdown (v 1 at tsd2; v 2 at tsd1).
detailed description L99PM62GXP 16/102 doc id 17639 rev 4 2.1.5 voltage regulator behaviour figure 7. voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp- down conditions 2.2 operating modes the L99PM62GXP can be operated in 4 different operating modes: active flash v 1 standby v bat standby a cyclic monitoring of wake-up inputs and a periodic interrupt/wake-up by timer is available in standby modes. 2.2.1 active mode all functions are available and the device is controlled by the st spi interface. 9 v >9@ 9 >9@ 1uhvhw >9@ 9 1 9 '3 9 325 &rog6wduwelwlv vhw xv 9 57+ +ljk /rz 3rzhurq 5hvhwwkuhvkrog 9 idlo ,iw!wyvkruw 9vkruwghwhfwhg ? 9edwwvwdqge\ 9 idlo elwlvvhw 9 vxy elwlvwvhw ww xy w 55 w 55 w!w xy 1r5hvhwjhqhudwhg w!w xy 6shflilfdwlrq3dudphwhuv w ug w ug 9 689 ,qdfwlyh $fwlyh ,qdfwlyh 5hdg &ohdu)62%lw 9 1 &rqwuro5hjlvwhuvduhvhwwrghidxowydoxhv 'lvdeohg 'lvdeohg 9 $%6plq +ljk=*urxqghg &rqwuro5hjlvwhuvduhvhwwrghidxow ydoxhv )dlo6dih2xwsxw w!w yidlo w xy 9xqghuyrowdjhilowhuwlph w yidlo 9idloilowhuwlph w yvkruw 9vkruwilowhuwlph w 55 5hvhwsxovhuhdfwlrqwlph w ug 5hvhwsxovhgxudwlrq 9 v89 9vxqghuyrowdjhwkuhvkrog 9 sru 9vsrzhu rquhvhwwkuhvkrog 9 uwk 9uhvhwwkuhvkrog 9 idlo 9idlowkuhvkrog $*9
L99PM62GXP detailed description doc id 17639 rev 4 17/102 2.2.2 flash mode to program the system microcontroller, the l99pm62 can be operated in flash mode where the internal watchdog is disabled. this mode can also be used for software debugging. except for the disabled watchdog, the flash mode is identical to active mode and all device features are available. a transition from flash mode to v 1stby or v batstby is not possible. the mode can be entered if one of the following conditions is applied: v txdl > v flash v txdc > v flash at exit from flash mode (v txd < v flash ) no nreset pulse is generated and the watchdog starts with a long open window. note: setting both txdl and txdc to high voltage levels (> v flash ) is not allowed. communication at the respective txd pin is not possible. 2.2.3 v 1 standby mode the transition from active mode to v 1 standby mode is controlled by spi. to supply the micro controller in a low power mode, the voltage regulator 1 (v 1 ) remains active. in order to reduce the current consumption, the regulator goes in low current mode as soon as the supply current of the microcontroller goes below the i cmp current threshold. at this transition, the l99pm62 also deactivates the internal watchdog. relay outputs, lin and can transmitters is switched off in v 1 standby mode. high-side outputs and the v 2 regulator remain in the configuration programmed prior to the standby command. a cyclic supply of external contacts and a synchronized monitoring of the contact state can be activated and configured by spi. in v 1 standby mode various wake up sources can be individually programmed. each wake up event puts the device into active mode and forces the rxdl/nint pin to a low level indicating the wake-up condition to the microcontroller. after power on reset (por) all wake up sources are activated by default except the periodic interrupt/wake timer. with the interrupt timer the micro controller can be forced from ?stop? to ?run? after a programmable period. the rxdl/nint pin is forced low after the timer is elapsed. the L99PM62GXP enters active mode and is awaiting a valid watchdog trigger. both internal timers can be used for this feature. the interrupt timer (t int ) at pin rxdl/nint is only available in v 1 standby mode. note: inputs txdl, txdc and csn must be at high level or at high impedance in order to achieve minimum standby current in v 1 standby mode. inputs di and clk must be at gnd or at high impedance to achieve minimum standby current in v 1 standby mode.
detailed description L99PM62GXP 18/102 doc id 17639 rev 4 interrupt the interrupt signal (linked to rxdl/nint internally) indicates a wake-up event from v 1 standby mode. in case of a wake-up by wake-up inputs, activity on lin or can, spi access or timer-interrupt the nint pin is pulled low for 56 s. in case of v 1 standby mode and (i v1 > i cmp ), the device remains in standby mode, the v 1 regulator switches to high current mode and the watchdog starts. no interrupt signal is generated. 2.2.4 v bat standby mode the transition from active mode to v bat standby mode is initiated by an spi command. in v bat standby mode, the v 1 voltage regulator, relay outputs, lin and can transmitters are switched off. high-side outputs and the v 2 regulator remain in the configuration programmed prior to the standby command. in v bat standby mode the current consumption of the L99PM62GXP is reduced to a minimum level. note: inputs txdl, txdc and csn must be terminated to gnd in v bat standby to achieve minimum standby current. this can be achieved with the internal esd protection diodes of the microcontroller (microcontroller is not supplied in this mode; v 1 is pulled to gnd). 2.2.5 wake up from standby modes a wake-up from standby mode switches the device to active mode. this can be initiated by one or more of the following events: to prevent the system from a deadlock condition (no wake up possible) a configuration where the periodic timer interrupt and wake up by lin and hs can are disabled, is not table 3. wake up sources wake up source description lin bus activity can be disabled by spi can bus activity can be disabled by spi level change of wu1 - 3 can be individually configured or disabled by spi i v1 > i cmp device remains in v 1 standby mode but watchdog is enabled (if i cmp = 0) and the v 1 regulator goes into high current mode (increased current consumption). no interrupt is generated. timer interrupt / wake up of c by timer programmable by spi ?v 1 standby mode: device wakes up and interrupt signal is generated at rxdl/nint when programmable time-out has elapsed ?v bat standby mode: device wakes up, v 1 regulator is turned on and nreset signal is generated when programmable time-out has elapsed spi access always active (except in v bat standby mode) wake up event: csn is low and first rising edge on clk
L99PM62GXP detailed description doc id 17639 rev 4 19/102 allowed. the default configuration is entered for all wake-up sources in case of such an invalid setting. all wake-up events from v 1 standby mode (except i v1 > i cmp ) are indicated to the microcontroller by a low-pulse at rxdl/nint (duration: 56 s). wake-up from v 1 standby by spi access might be used to check the interrupt service handler. 2.2.6 wake-up inputs the de-bounced digital inputs wu1 to wu3 can be used to wake up the L99PM62GXP from standby modes. these inputs are sensitive to any level transition (positive and negative edge) for static contact monitoring, a filter time of 64 s is implemented at wu1-3. the filter is started when the input voltage passes the specified threshold. in addition to the continuous sensing (static contact monitoring) at the wake up inputs, a cyclic sense functionality is implemented. this feature allows periodical activation of the wake-up inputs to read the status of the external contacts. the periodical activation can be linked to timer1 or timer2 (see section 2.2.7: cyclic contact supply ). the input signal is filtered with a filter time of 16 s after a programmable delay (80 s or 800 s) according to the configured timer on-time. a wake-up is processed if the status has changed versus the previous cycle. the outputs out_hs and out1-4 can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up inputs. if the wake-up inputs are configured for cyclic sense mode the input filter timing and input filter delay ( wux_filt in control register 2) must correspond to the setting of the high-side output which supplies the external contact switches (outx in control register 0). in standby mode, the inputs wu1-3 are spi configurable for pull-up or pull-down current source configuration according to the setup of the external. in active mode the inputs have a pull down resistor. in active mode, the input status can be read by spi (status register 2). static sense should be configured (control register 2) before the read operation is started (in cyclic sense configuration, the input status is updated according to the cyclic sense timing; therefore, reading the input status in this mode may not reflect the actual status). 2.2.7 cyclic contact supply in v 1 standby and v bat standby modes, any high-side driver output (out1..4, ouths) can be used to periodically supply external contacts. the timing is selectable by spi timer 1: period is x s. the on-time is 10 ms resp. 20 ms: with x {1, 2, 3, 4 s} timer 2: period is x ms. the on-time is 100 s resp. 1ms: with x {10, 20, 50, 200 ms} 2.2.8 timer interrupt / wake-up of microcontroller by timer during standby modes the cyclic wake up feature, configured via spi, allows waking up the c after a programmable timeout according to timer1 or timer2.
detailed description L99PM62GXP 20/102 doc id 17639 rev 4 from v 1 standby mode, the L99PM62GXP wakes up (after the selected timer has elapsed) and sends an interrupt signal (via rxdl/nint pin) to the c. the device enters active mode and the watchdog is started with a long open window. the microcontroller can send the device back into v 1 standby after finishing its tasks. from v bat standby mode, the L99PM62GXP wakes up (after the selected timer has elapsed), turns on the v 1 regulator and provides an nreset signal to the c. the device enters active mode and the watchdog is started with a long open window. the microcontroller can send the device back into v bat standby after finishing its tasks. 2.3 functional overview (truth table) table 4. functional overview (truth table) function comments operating modes active mode v 1 -standby static mode (cyclic sense) v bat -standby static mode (cyclic sense) voltage-regulator, v 1 v out = 5 v on on (1) off voltage-regulator, v 2 v out = 5 v on/ off (2) on (2) / off on (2) / off reset-generator on on off window watchdog v 1 monitor on off (on: i_v 1 > i cmp - threshold and i cmp =0) off wake up off active (3) active (3) hs-cyclic supply oscillator time base on / off on (2) / off on (2) / off relay driver on off off operational amplifiers on off off lin lin 2.1 on off (4) off (4) hs_can on off (4) off (4) fso (if configured by spi), active by default fail safe output out3/fso off (5) out3/fso off (5) out3/fso off (5) oscillator on (6) (6) vs-monitor on (7) (7) 1. supply the processor in low current mode. 2. only active when selected via spi. 3. unless disabled by spi. 4. the bus state is internally stored when going to standby m ode. a change of bus state leads a wake-up after exceeding of internal filter time (if wake-up by lin or can is not disabled by spi). 5. on in fail-safe condition: if standby m ode is entered with active fail safe mode, the output remains on in standby mode. 6. activation = on if cyclic sense is selected. 7. cyclic activation = pulsed on during cyclic sense.
L99PM62GXP detailed description doc id 17639 rev 4 21/102 figure 8. operating modes 2.4 configurable window watchdog during normal operation, the watchdog monitors the micro controller within a programmable trigger cycle: (10 ms, 50 ms, 100 ms, 200 ms) in v bat standby and flash program modes, the watchdog circuit is automatically disabled. in v 1 standby mode a wake up by timer is programmable in order to wake up the c (see section 2.2.8: timer interrupt / wake-up of microcontroller by timer ). after wake-up, the watchdog starts with a long open window. after serving the watchdog, the c may send the device back to v 1 standby mode. $fwlyh 0rgh 921 5hvhw*hqhudwrudfwlyh :dwfkgrjdfwlyh 96wdqge\ 0rgh 921 5hvhw*hqhudwrudfwlyh :dwfkgrj 2))li,y, fps ru,&03 9edw6wdqge\ 0rgh 92)) 5hvhw*hqhudwru2))1uhvhw orz :dwfkgrj2)) :dnhxs (yhqw :dnhxs (yhqw 63,frppdqg 9edwvwduwxs $oouhjlvwhuv 6hwwrghidxow &kls5hvhwelw*65elw dfwlyh 9v!9sru [7khupdo6kxwgrzq76' 25 [:'idlo )odvk0rgh :dwfkgrj2)) 9 7;'/ !9 iodvk 25 9 7;'& !9 iodvk 9 7;'/ !9 iodvk 25 9 7;'& !9 iodvk 9 7;'/ 9 iodvk $1' 9 7;'& 9 iodvk 9 7;'/ !9 iodvk 25 9 7;'& !9 iodvk 63,frppdqg 25 [7khupdo6kxwgrzq 25 9vkruwwr*1' 99irupvdiwhuvzlwfk21 25 [:')dloxuh $*9
detailed description L99PM62GXP 22/102 doc id 17639 rev 4 after power-on or standby mode, the watchdog is started with a long open window (65 ms nominal). the long open window allows the micro controller to run its own setup and then to trigger the watchdog via the spi. the trigger is processed when the csn input becomes high after the transmission of the spi word. writing ?1? to the watchdog trigger bit terminates the long open window and start the window watchdog (the timing is programmable by spi). subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer to figure 29 ). a correct watchdog trigger signal immediately starts the next cycle. after 8 watchdog failures in sequence, the v 1 regulator is switched off for 200ms. if subsequently, 7 additional watchdog failures occur, the v 1 regulator is completely turned off and the device goes into v bat standby mode until a wakeup occurs. in case of a watchdog failure, the outputs (relx, outx, v 2 ) are switched off and the device enters fail-safe mode (i.e. all control registers are set to default values except the ?out3 control bit?). the following diagrams illustrate the watchdog behavior of the l99pm62. the diagrams are split into 3 parts. first diagram shows the functional behavior of the watchdog without any error. the second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. third diagram shows the transition in and out of flash mode. all 3 diagrams can be overlapped to get all the possible state transitions under all circumstances. for a better readability, they were split in normal operating, operating with errors and flash mode. figure 9. watchdog in normal operating mode (no errors) :' 2)) orqj rshq zlqgrz :lqgrz 0rgh sursshuwuljjhulq :lqgrzprgh 75,* ?
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L99PM62GXP detailed description doc id 17639 rev 4 23/102 figure 10. watchdog with error conditions figure 11. watchdog in flash mode 2.4.1 change watchdog timing there are 4 programmable watchdog timings available, which represent the nominal trigger time in window mode. to change the watchdog timing, a new timing has to be written by spi. the new timing gets active with the next valid watchdog trigger. the following figures illustrate the sequence, which is recommended to use, changing the timing within long open window and within window mode. :' 2)) orqj rshq zlqgrz :lqgrz 0rgh sursshuwuljjhulq :lqgrzprgh 75,* ?
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detailed description L99PM62GXP 24/102 doc id 17639 rev 4 figure 12. change watchdog timing within long open window figure 13. change watchdog timing within window mode if the device is in fail-safe mode, the control registers are locked for writing. to change the watchdog timing out of fail-safe mode, first the fail-safe condition must be solved, respective confirmed from the microcontroller. afterwards the new watchdog timing can be programmed using the sequence from figure 14 . since the actions to remove, a fail-safe condition can differ from the root cause of the fail safe the following diagram shows the general procedure how to change the watchdog timing out of fail-safe mode. figure 15 shows the procedure to change watchdog timing with a previous watchdog failure, since this is a special fail-safe scenario. orqjrshqzlqgrz zlqgrzprgh >wlplqjdvsurjudpphglqsuhylrxv63,frppdqghjpv@ &61 zulwhrshudwlrq &wuo5hj :'7lph >hjpv@ )hhgedfn )62 zulwhrshudwlrqdffhswhg zulwhrshudwlrq &wuo5hj7ulj )hhgedfn fkhfn)62 fkdqjhwlplqjiru:' uhdgrshudwlrq &wuo5hj )hhgedfn fkhfn)62 fkhfn:'wlph zulwhrshudwlrq &wuo5hj7ulj :'wlplqj>hjpv@ 63, &rppdqg 63, )hhgedfn :dwfkgrj 0rgh $*9 zlqgrzprgh>pv@ zulwhrshudwlrq &wuo5hj :'7lph >hjpv@ &61 zulwhrshudwlrq &wuo5hjsurshuwuljjhu uhdgrshudwlrq &wuo5hj zulwhrshudwlrq &wuo5hjsurshuwuljjhu :'wlph>pv@ zlqgrzprgh>pv@ zulwhrshudwlrq &wuo5hjsursshuwuljjhu )hhgedfn )62 zulwhrshudwlrqdffhswhg )hhgedfn fkhfn)62 fkdqjhwlplqjiru:' )hhgedfn fkhfn)62 fkhfn:'wlph :'wlph>pv@ 63, &rppdqg 63, )hhgedfn :dwfkgrj 0rgh $*9
L99PM62GXP detailed description doc id 17639 rev 4 25/102 figure 14. general procedure to change watchdog timing out of fail safe mode figure 15. change watchdog timing out of fail safe mode (watchdog failure) 2.5 fail safe mode 2.5.1 single failures L99PM62GXP enters fail safe mode in case of: watchdog failure v 1 turn on failure ?v 1 short (v 1 < v 1fail for t > t v1short ) v 1 undervoltage (v 1 < vrth for t > t uv1 ) thermal shutdown tsd2 spi failure ? di stuck to gnd or v cc (spi frame = ?00 00 00? or ?ff ff ff?) $*9 $fwlrqvwrh[lw )dlovdih0rgh 3urfhgxuhwr:ulwhqhz:dwfkgrjwlplqj orqjrshqzlqgrz &61 zlqgrzprgh >wlplqjdvsurjudpphglqsuhylrxv63,frppdqghjpv@ zulwhrshudwlrq &wuo5hj :'7lph >hjpv@ )hhgedfn )62 zulwhrshudwlrqdffhswhg zulwhrshudwlrq &wuo5hj7ulj )hhgedfn fkhfn)62 fkdqjhwlplqjiru:' uhdgrshudwlrq &wuo5hj )hhgedfn fkhfn)62 fkhfn:'wlph zulwhrshudwlrq &wuo5hj7ulj :'wlph>hjpv@ )dlo6dih0rghdfwlyh )dlo6dih0rghlqdfwlyh 63, &rppdqg 63, )hhgedfn :dwfkgrj 0rgh $*9 3urfhgxuhwr:ulwhqhz:dwfkgrjwlplqj $fwlrqvwrh[lw )dlovdih0rgh zulwhrshudwlrq &wuo5hj :'7lph >hjpv@ )hhgedfn )62 zulwhrshudwlrqeorfnhg &61 zulwhrshudwlrq &wuo5hj7ulj )hhgedfn )62 surylghsursshuwuljjhu uhdgrshudwlrq dq\ydolgdgguhvv )hhgedfn fkhfn)62 txlwidlovdihprgh zulwhrshudwlrq &wuo5hj :'7lph >hjpv@ )hhgedfn )62 zulwhrshudwlrqdffhswhg zulwhrshudwlrq &wuo5hj7ulj )hhgedfn fkhfn)62 fkdqjhwlplqjiru:' uhdgrshudwlrq &wuo5hj )hhgedfn fkhfn)62 fkhfn:'wlph orqjrshqzlqgrz zlqgrzprgh>pv@ :'wlph>pv@ zlqgrzprgh >wlplqjdvsurjudpphglqsuhylrxv63,frppdqghjpv@ zulwhrshudwlrq &wuo5hjsurshuwuljhu :'wlph>hjpv@ )dlo6dih0rghdfwlyh )dlo6dih0rghlqdfwlyh 63, &rppdqg 63, )hhgedfn :dwfkgrj 0rgh
detailed description L99PM62GXP 26/102 doc id 17639 rev 4 the fail safe functionality is also available in v 1 standby mode. during v 1 standby mode the fails safe mode is entered in the following cases: v 1 undervoltage (v 1 < vrth for t > t uv1 ) watchdog failure (if watchdog still running due to i v1 > i cmp ) thermal shutdown tsd2 in fail safe mode the l99pm62 returns to a default. the fail safe condition is indicated to the remaining system in the global status register. the conditions during fails safe mode are: all outputs are turned off all control registers are set to default values (except out3/fso configuration) write operations to control registers are blocked until the fail safe condition is cleared (see table 5 ) lin and hs can transmitter, opamps and spi remain on corresponding failure bits in status registers are set. fso bit (bit 0 global status register) is set out3/fso is activated if configured as fail safe output if out3 is configured as fso, the internal fail safe mode can be monitored at out3 (high- side driver is turned on in fail-safe mode). self protection features for out3 when configured as fso are active (see section 3.3: high-side driver outputs ). out3 is configured as fail safe output by default. it can be configured to normal high-side driver operation by spi. it this case, the configuration remains until vs power on. if the fail safe mode was entered it keeps active until the fail safe condition is removed and the fail safe was read by spi. depending on the root cause of the fail safe operation, the actions to exit fail safe mode are as shown in the following table. table 5. fail safe conditions and exit modes failure source failure condition diagnosis exit from fail-safe mode c (oscillator) watchdog early write failure or expired window fail-safe = 1 wdfail = n+1 trig = 1 during lowi and read fail-safe bit v 1 short at turn-on fail-safe = 1 forced sleep tsd2/shtv 1 = 1 read&clear sr3 after wake undervoltage fail-safe = 1 v 1fail = 1 (1) v 1 > vrth read fail-safe bit temperature t j > tsd2 fail-safe = 1 tw = 1 tsd1 = 1 tsd2 = 1 t j < tsd2 read&clear sr3 spi di short to gnd or v cc fail-safe = 1 valid spi command 1. if v 1 < v 1fail (for t > t v1fail ) the fail-safe bit is located in the global status register (bit 0).
L99PM62GXP detailed description doc id 17639 rev 4 27/102 2.5.2 multiple failures ? entering forced v bat standby mode if the fail-safe condition persists and all attempts to return to normal system operation fail, the l99pm62 enters the forced v bat standby mode in order to prevent damage to the system. the forced v bat standby mode can be terminated by any regular wake-up event. the root cause of the forced v bat standby is indicated in the spi status registers the forced v bat standby mode is entered in case of: multiple watchdog failures: forced sleep wd = 1 (15x watchdog failure) multiple thermal shutdown 2: forced sleep tsd2/shtv1 = 1 (7 x tsd2) v 1 short at turn-on: forced sleep tsd2/shtv1 = 1 (v 1 < v 1fail for t > t v1fail ) figure 16. example: exit fail safe mode from watchdog failure table 6. persisting fail safe conditions and exit modes failure source failure condition d iagnosis exit from fail-safe mode c (oscillator) 15 consecutive watchdog failures fail-safe = 1 forcedsleepwd = 1 wake-up trig = 1 during lowi read & clear sr3 v 1 short at turn-on fail-safe = 1 forcedsleeptsd2/shtv 1 = 1 read&clear sr3 after wake-up temperature 7 times tsd2 fail-safe = 1 tw = 1 tsd1 = 1 tsd2 = 1 forcedsleeptsd2/shtv 1 = 1 read&clear sr3 after wake-up zulwhrshudwlrq &wuo5hj :'7lph >hjpv@ )hhgedfn )62 zulwhrshudwlrqeorfnhg &61 zulwhrshudwlrq &wuo5hj7ulj )hhgedfn )62 surylghsursshuwuljjhu uhdgrshudwlrq dq\ydolgdgguhvv )hhgedfn fkhfn)62 txlwidlovdihprgh orqjrshqzlqgrz zlqgrzprgh )dlo6dih0rghdfwlyh )dlo6dih0rghlqdfwlyh 63, &rppdqg 63, )hhgedfn :dwfkgrj 0rgh $*9
detailed description L99PM62GXP 28/102 doc id 17639 rev 4 2.6 reset output (nreset) if v 1 is turned on and the voltage exceeds the v 1 reset threshold, the reset output ?nreset? is pulled up by internal pull up resistor to v 1 voltage after a reset delay time (t rd ). this is necessary for a defined start of the micro controller when the application is switched on. since the nreset output is realized as an open drain output it is also possible to connect an external nreset open drain nreset source to the output. it must be considered that as soon the nreset is released from the l99pm62 the watchdog timing starts. a reset pulse is generated in case of: v 1 drops below vrth (configurable by spi) for t > t uv1 watchdog failure note: an external pull-up resistor (1k ) to v 1 is recommended in order to ensure i load 1 > i cmp during reset condition 2.7 operational amplifiers the operational amplifiers are especially designed to be used for sensing and amplifying the voltage drop across ground connected shunt resistors. therefore the input common mode range includes -0.2 v to 3 v. the operational amplifiers are designed for -0.2 v to +3 v input voltage swing and rail-to-rail output voltage range. all pins (positive, negative and outputs) are available to be able to operate in non-inverting and inverting mode. both operational amplifiers are on-chip compensated for stability over the whole operating range within the defined load impedance. the operational amplifiers may also be used to setup an additional high current voltage source with an external pass element. refer to section 2.1.3 for a detailed description. 2.8 lin bus interface features speed communication up to 20 kbit/s. lin 2.1 compliant (saej2602 compatible) transceiver. function range from +40 v to -18 v dc at lin pin. gnd disconnection fail safe at module level. off mode: does not disturb network. gnd shift operation at system level. micro controller interface with cmos compatible i/o pins. internal pull up resistor. internal high-side switch to disconnect master pull-up resistor in case of short circuit of bus signal. esd and transient immunity according to iso7637 and en / iec61000-4-2. matched output slopes and propagation delay.
L99PM62GXP detailed description doc id 17639 rev 4 29/102 in order to further reduce the current consumption in standby mode, the integrated lin bus interface offers an ultra low current consumption. note: use of master pull-up switch is optional. 2.8.1 error handling the L99PM62GXP provides the following 3 error handling features which are not described in the lin spec. v 2.1 , but are realized in different stand alone lin transceivers / micro controllers to switch the application back to normal operation mode. at v s > vpor (i.e. vs power-on reset threshold), the lin transceiver is enabled. the lin transmitter is disabled in case of the following errors: dominant txdl time out lin permanent recessive thermal shutdown 1 v s over/undervoltage the lin receiver is not disabled in case of any failure condition. dominant txdl time out if txdl is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. this feature can be disabled via spi. permanent recessive if txdl changes to dominant (low) state but rxdl signal does not follow within 40 s the transmitter is disabled, the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. permanent dominant if the bus state is dominant (low) for more than 12 ms a permanent dominant status is detected. the status bit is latched and can be read and optionally cleared by spi. the transmitter is not disabled. 2.8.2 wake up (from lin) in standby mode the L99PM62GXP can receive a wake up from lin bus. for the wake up feature the L99PM62GXP logic differentiates two different conditions. normal wake up normal wake up can occur when the lin transceiver was set in standby mode while lin was in recessive (high) state. a dominant level at lin for t linbus , switches the L99PM62GXP to active mode. wake up from short to gnd condition if the lin transceiver was set in standby mode while lin was in dominant (low) state, recessive level at lin for t linbus , switches the L99PM62GXP to active mode. note: a wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode.
detailed description L99PM62GXP 30/102 doc id 17639 rev 4 2.8.3 lin pull-up the master node pull-up resistor (1 k ) can be connected to v s using the internal lin_pu high-side switch. this high-side switch can be controlled by spi in order to allow disconnection of the pull-up resistor in case of lin bus short to gnd conditions. figure 17. lin master node confi guration using lin_pu (optional) lin_pu high-side driver characteristics: activated by default and can be turned off by spi command (cr4). remains active in standby modes. switch off only in case of over temperature (tsd2 = thermal shutdown #2). no over current protection. typical r ds on, 10 . 2.9 high speed can bus transceiver general requirements communication speed up to 1 mbit/s. iso 11898-2 and iso 11898-5 compliant sae j2284 compliant function range from -27 v to +40 v dc at can pins. gnd disconnection fail safe at module level. gnd shift operation at system level. micro controller interface with cmos compatible i/o pins. esd and transient immunity according to iso7637 and en / iec61000-4-2 matched output slopes and propagation delay split output pin for stabilizing the recessive bus level receive-only mode available frqwuro 9v /,1 frqwuro n /,1 *qg n 0dvwhuqrgh sxooxs /,138 7 6: $*9
L99PM62GXP detailed description doc id 17639 rev 4 31/102 in order to further reduce the current consumption in standby mode, the integrated can bus interface offers an ultra low current consumption. 2.9.1 can error handling the L99PM62GXP provides the following 4 error handling features which are not described in the iso 11898-2/iso 11898-5, but are realized in different stand alone can transceivers/micro controllers to switch the application back to normal operation mode. at v s > vpor (i.e. v s power-on reset threshold), the can transceiver is enabled. it remains enabled also in case of v s overvoltage and undervoltage conditions. the can transmitter is disabled only in case of the following errors: dominant txdc time out can permanent recessive rxdc permanent recessive thermal shutdown 1 the can receiver is not disabled in case of any failure condition. dominant txdc time out if txdc is in dominant state (low) for t > t dom(txd) the transmitter is disabled, status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. can permanent recessive if txdc changes to dominant (low) state but can bus does not follow for 4 times, the transmitter is disabled, status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. can permanent dominant if the bus state is dominant (low) for t > t can a permanent dominant status is detected. the status bit is latched and can be read and optionally cleared by spi. the transmitter is not disabled. rxdc permanent recessive if rxdc pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. therefore, if rxdc does not follow txdc for 4 times the transmitter is disabled. the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. 2.9.2 wake up (from can) when the L99PM62GXP is in standby mode with can wake up option enabled, the can bus traffic is detected. for the wake up feature the L99PM62GXP logic differentiates different conditions. during v 1 standby mode rxdc output is kept at recessive level. independent from the wakeup pattern selected and independent from the previous standby mode, the rxdc reflect immediately the bus state after the wakeup. this feature allows implementation of a ?partial networking? functionality controlled by the system microcontroller.
detailed description L99PM62GXP 32/102 doc id 17639 rev 4 normal pattern wake up normal pattern wake up can occur when can pattern wake up option is enabled and the can transceiver was set in standby mode while can bus was in recessive (high) state or dominant (low) state. in order to wake up the L99PM62GXP, the following criteria must be fulfilled: the can interface wake-up receiver must receive a series of two consecutive valid dominant pulses, each of which must be longer than 2 s the distance between 2 pulses must be longer than 2 s. the two pulses must occur within a time frame of 1.0 ms wake up from short to gnd condition even if can pattern wake up option is enabled, but the can transceiver was set in standby mode after a qualified permanent dominant state, recessive level at can, switches the L99PM62GXP to active mode. no pattern wake up if the can pattern wake up option is disabled, any transition either dominant (low) state to recessive (high) state or recessive (high) state to dominant (low) state switches the L99PM62GXP to active mode (after a filtering time of 2 s). note: a wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode. figure 18. can wake up capabilities note: pictures above illustrate the wake up behaviour from v 1 standby mode. for wake up from v bat standby mode an nreset pulse is generated instead of the rxdl (interrupt) signal. 1rsdwwhuq:dnhxs 3dwwhuq:dnhxs $&7,9( 67$1'%< $&7,9( &$15; 67$7( !xv !xv !xv pv 6wdqgdugfdqsdwwhuqzdnhxs $&7,9( 67$1'%< $&7,9( &$15; 67$7( !xv !xv !xv pv &$1sdwwhuqzdnhxszlwkgrplqdqwehiruh6wdqge\ $&7,9( 67$1'%< $&7,9( &$15; 67$7( !shupdqqhqwgrplqdqwilowhuwlph !xv &$1sdwwhuqzdnhxszlwkshupdqhqwgrplqdqw $&7,9( 67$1'%< $&7,9( &$15; 67$7( !xv 6wdqgdugzdnhxs $&7,9( 67$1'%< $&7,9( &$15; 67$7( !shupdqqhqw grplqdqwilowhuwlph !xv &$1zdnhxszlwkshupdqhqwgrplqdqw $&7,9( 67$1'%< $&7,9( &$15; 67$7( !xv &$1zdnhxszlwkgrplqdqwehiruh6wdqge\ $*9
L99PM62GXP detailed description doc id 17639 rev 4 33/102 2.9.3 can sleep mode during active mode it is possible to deactivate the can transceiver with a dedicated spi command (cr4, can_act = 0). the can transceiver remains deactivated until it is activated again. with a deactivated can the receiver input termination network is disconnected from the bus and the canh, canl bus lines is driven to gnd. the split output is also deactivated in this case. 2.9.4 can receive only mode with the can_rec_only bit in control register 4 it is possible to disable the can transmitter in active mode. in this mode it is possible to listen to the bus but not sending to it. the receiver termination network is still activated in this mode. 2.9.5 can looping mode if the can_loop_en bit in control register 4 is set the txdc input is mapped directly to the rxdc pin. this mode can be used in combination with the can receive only mode, to run diagnosis for the can protocol handler of the micro controller. 2.10 serial peripheral interface (st spi standard) a 24 bit spi is used for bi-directional communication with the micro controller. during active mode, the spi triggers the watchdog controls the modes and status of all L99PM62GXP modules (incl. input and output drivers) provides driver output diagnostic provide L99PM62GXP diagnostic (incl. overtemperature warning, L99PM62GXP operation status) the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. this device is not limited to micro controller with a built-in spi. only three cmos-compatible output pins and one input pin is needed to communicate with the device. a fault condition can be detected by setting csn to low. if csn = 0, the do-pin reflects the global error flag (fault condition) of the device. chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal activates the output driver and a serial communication can be started. the state during csn = 0 is called a communication frame. if csn = low for t > t csnfail the do output is switched to high impedance in order to not block the signal line for other spi nodes.
detailed description L99PM62GXP 34/102 doc id 17639 rev 4 serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di is sampled at the rising edge of the clk signal and shifted into an internal 24 bit shift register. at the rising edge of the csn signal the contents of the shift register is transferred to data input register. the writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame is ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame. note: due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ic's is recommended. serial data out (do) the data output driver is activated by a logical low level at the csn input and goes from high impedance to a low or high level depending on the global error flag (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin transfers the content of the selected status register into the data out shift register. each subsequent falling edge of the clk shifts the next bit out. serial clock (clk) the clk input is used to synchronize the input and output serial bit streams. the data input (di) is sampled at the rising edge of the clk and the data output (do) changes with the falling edge of the clk signal. the spi can be driven with a clk frequency up to 1mhz.
L99PM62GXP protection and diagnosis doc id 17639 rev 4 35/102 3 protection and diagnosis 3.1 power supply fail over and under-voltage detection on vs 3.1.1 v s overvoltage if the supply voltage vs reaches the over voltage threshold (v sov ): outputs outx, relx and lin are switched to high impedance state (load protection). can is not disabled. recovery of outputs when the overvoltage condition disappears is depending on the setting of vlockout_en bit in control register 4. ? vlockout_en = 1: outputs are off until read and clear sr3. ? vlockout_en = 0: outputs switch automatically on when overvoltage condition disappears. the over voltage bit is set and can be cleared with a ?read and clear? command. the overvoltage bit is removed automatically if vlockout_en = 0 and the overvoltage condition disappears. outputs rel1,2 can be excluded from a shutdown in case of overvoltage by spi (lsovuv_ shutdown_en in cr4) 3.1.2 vs undervoltage if the supply voltage vs drops below the under voltage threshold voltage (v suv ) outputs outx, relx and lin are switched to high impedance state (load protection). can is not disabled. recovery of outputs when the undervoltage condition disappears is depending on the setting of vlockout_en bit. vlockout_en = 1: outputs are off until read and clear sr3. vlockout_en = 0: outputs switch on automatically when undervoltage condition disappears. the undervoltage bit is set and can be cleared with a ?read and clear? command. the undervoltage bit is removed automatically if vlockout_en = 0 and the undervoltage condition disappears outputs rel1,2 can be excluded from a shutdown in case of undervoltage by spi (lsovuv_shutdown_en in cr4)
protection and diagnosis L99PM62GXP 36/102 doc id 17639 rev 4 figure 19. over voltage and under voltage protection and diagnosis $fwlyh 0rgh 6wdqge\0rghv gxulqjf\folfvhqvh 9v8yhuyrowdjh 6kxwgrzq $oorxwsxwvkljk,pshgdqfh h[fhsw5(/rxwsxwvli /6bryxy 'ldjqrvlv89 9v2yhuyrowdjh 6kxwgrzq $oorxwsxwvkljk,pshgdqfh h[fhsw5(/rxwsxwvli /6bryxy 'ldjqrvlv29 9v2yhuyrowdjh 9v!9vry 9v8qghuyrowdjh 9v9vxy 9v9vry$1'?5hdgdqg&ohdu? 25 9v9vry$1'9orfnrxw 9v!9vxy$1'?5hdgdqg&ohdu? 25 9v!9vxy$1'9orfnrxw $*9
L99PM62GXP protection and diagnosis doc id 17639 rev 4 37/102 3.2 temperature warning and thermal shutdown figure 20. thermal shutdown protection and diagnosis note: the thermal state machine recovers the same state were it was before entering standby mode. in case of a tsd2 it enters tsd1 state. $fwlyh 0rgh 6wdqge\0rghv gxulqjf\folfvhqvh 7hpshudwxuh :duqlqj 'ldjqrvlv7: 76' $oorxwsxwvh[fhsw9rii 'ldjqrvlv76' 7m!76' ?5hdgdqg&ohdu? 25 3rzhurquhvhw 76' $oorxwsxwvrii 9riiiruvhf 'ldjqrvlv76' 7m!76' 9edwvwe\ $oorxwsxwvlqfo9rii [76' :dnhxshyhqw 3rzhurquhvhw ?5hdgdqg&ohdu? 25 3rzhurquhvhw 7m!7z 7!vhf 3rzhu2q5hvhw $oorxwsxwvlqfo9rii 9v!9sru $*9
protection and diagnosis L99PM62GXP 38/102 doc id 17639 rev 4 3.3 high-side driver outputs the component provides a total of 4 high-side outputs out1 to 4, (7 typical at 25c) to drive e.g. led's or hall sensors and 1 high-side output out_hs with 1 typical at 25 c). the high-side outputs switch off in case of: v s over and undervoltage overcurrent overtemperature (tsd1) with pre warning (a) in case of overload or over temperature (tsd1) condition, the drivers switches off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case over/under voltage condition, the drivers is switched off. the according status bit is latched and can be read and optionally cleared by spi. if the vlockout bit (control register 4) is set to ?1? the drivers remain off until the status is cleared. if the vlockout bit is set to ?0? the drivers switches on automatically if the error condition disappears. in case of open-load condition, the according status register is latched. the status can be read and optionally cleared by spi. the high-sides are not switched off. for out_hs the auto recovery feature (outhsrec bit control register 4) can be enabled. if this bit is set to ?1? the driver is automatically restart from a overload condition. this overload recovery feature is intended for loads which have an initial current higher than the over current limit of the output (e.g. inrush current of cold light bulbs). during auto recovery mode the over current status bit can not be read from spi. the device itself can not distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. as an example, the micro controller can switch on light bulbs by setting the over current recovery bit for the first 50ms. after clearing the recovery bit, the output is automatically disabled if the overload condition still exists. in case of a fail safe condition, the high-side drivers are switched off. the control bits are set to default values. (except out3/fso if it is used as a high-side driver output) note: the maximum voltage and current applied to the high-side outputs is specified in section 5.1: absolute maximum rating . appropriate external protection may be required in order to respect these limits under application conditions. each high-side driver can be driven whether with a pwm signal or with a internal timer. see ta ble 7 . for more details please refer to section 6.2: spi registers . a. except out3 when configured as fso. table 7. pwm configuration for high-side outputs high-side output pwm channel internal timer out1 pwm 1 timer 1 out2 pwm 2 timer 2 out3 pwm 3 -
L99PM62GXP protection and diagnosis doc id 17639 rev 4 39/102 the pwm 1 / 3 channels start a pwm period with the on phase, while the pwm 2 / 4 channels start with the off phase. in this way it is possible to use the 4 pwm channels in a phase shifted way. the figure 21 shows this feature with a duty cycle of 25% for both pwm channels. figure 21. phase shifted pwm 3.4 low-side driver outputs rel1, rel2 the outputs rel1, rel2 (r dson = 2 typical at 25 c) are specially designed to drive relay loads. the outputs provide an active output zener clamping (45 v typical) feature for the demagnetization of the relay coil, even though a load dump condition exists. for fail-safe reasons the relay drivers are linked with the fail safe operation: in case of entering the fail safe mode, the relay drivers switches off and the spi control bits are set to default (i.e. driver is off). the low-side drivers switch off in case of: v s over and undervoltage overcurrent overtemperature with pre warning in case of overload or overtemperature (tsd1) condition, the drivers switches off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. out4 pwm 4 timer 2 ouths pwm 3 / pwm 4 timer 1 / timer 2 table 7. pwm configuration for high-side outputs (continued) high-side output pwm channel internal timer 3:03hulrg 287 3:0[) 287 3:0[) $*9
protection and diagnosis L99PM62GXP 40/102 doc id 17639 rev 4 in case v s over/undervoltage condition, the drivers is switched off. the according status bit is latched and can be read and optionally cleared by spi. if the vlockout bit (control register 4) is set to ?1? the drivers remain off until the status is cleared. if the vlockout bit is set to ?0? the drivers is switched on automatically if the error condition disappears. with the lsovuv_shutdown_en bit (control register 4) the drivers can be excluded from a switch off in case of v s over/undervoltage. if the bit is set to ?1? the driver switches off, otherwise the drivers remain on. 3.5 spi diagnosis digital diagnosis features are provided by spi (for details please refer to section 6.2: spi registers . v 1 reset threshold programmable overtemperature including. pre warning open-load separately for each output stage except rel1/rel2 overload status separately for each output stage vs-supply over/under voltage v 1 and v 2 fail bit v 2 output short to gnd status of the wu1 to 3 wake-up sources (can, lin, spi, timer, wu1?3) chip reset bit (start from power-on reset) number of unsuccessful v 1 restarts after thermal shutdown number of sequential watchdog failures lin diagnosis (permanent recessive/dominant, dominant txd) can diagnosis (permanent recessive/dominant, dominant txd, recessive rxd) device state (wake-up from v1 standby or v bat standby) forced v bat standby after wd-fail, forced v bat standby after overtemperature watchdog timer state (diagnosis of watchdog) fail-safe status spi communication error
L99PM62GXP typical application doc id 17639 rev 4 41/102 4 typical application figure 22. typical application diagram ', +ljk6lgh 63, /2*,& :lqgrz :dwfkgrj 9v $*1' 9 :8 &61 &/. '2 287b+6 287 5(/ 5(/ :dnh8s ,1 +ljk6lgh /rz6lgh 2xwsxw&odps 9rowdjh 0rqlwru :dnh8s ,1 :8 7hps3uhzduqlqj 6kxwgrzq 8qghuyrowdjh 2yhuyrowdjh 6kxwgrzq /rz6lgh 2xwsxw&odps 0 9v 9edw &\folf&rqwdfw 0rqlwrulqj 0lfur frqwuroohu 9edw /,1 5['/1,17 7['/ 15(6(7 9rowdjh 5hjxodwru q) 9 q) 9v :dnh8s ,1 :8 +ljk6lgh +ljk6lgh +ljk6lgh /,1 /,138 23 23 23b287 ?&$'& /,1 hj%xoe /('+doo 6hqvru 3*1' +6&$1 &$1/ &$1+ &$1683 &$1 7['& 5['& ([whuqdo )dlo6dih /rjlf 9 n ([whuqdoordgv 9v 9rowdjh 5hjxodwru /,1frpsoldqw 6$(-frpsdwleoh ,62[ dqg6$(-frpsoldqw 23 23 23b287 287 287)62 287 hj/(' +doo6hqvru $*9
electrical specifications L99PM62GXP 42/102 doc id 17639 rev 4 5 electrical specifications 5.1 absolute maximum rating note: all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! loss of ground or ground shift with externally grounded loads: esd structures are configured for nominal currents only. if external loads are connected to different grounds, the current load must be limited to this nominal current. table 8. absolute maximum rating symbol parameter/test condition value [dc voltage] unit v s dc supply voltage / ?jump start? -0.3 to +28 v single pulse / t max < 400 ms ?transient load dump? -0.3 to +40 v v 1 stabilized supply voltage, logic supply -0.3 to (v 1 + 0.3) v v 1 < v s v v 2 stabilized supply voltage -0.3 to +28 v v di v clk v do v rxdl v nreset v rxdc logic input / output voltage range -0.3 to v 1 +0.3 v v txdc, v txdl , v csn multi level inputs -0.3 to v s +0.3 v v rel1, v rel2, low-side output voltage range -0.3 to +40 v v out1..4, v out_hs high-side output voltage range -0.3 to v s +0.3 v v wu1...3 wake up input voltage range -0.3 to v s +0.3 v v op1p, v op1m, v op2p, v op2m, opamp1 input voltage range opamp2 input voltage range -0.3 to v 1 +0.3 v v opout1, v opout2 analog output voltage range -0.3 to v s +0.3 v v lin, v linpu lin bus i/o voltage range -20 to +40 v i input current injection into v s related input pins 20 ma iout_inj current injection into v s related outputs 20 ma v cansup can supply -0.3 to +5.25 v v canh, v canl, v split can bus i/o voltage range -27 to +40 v
L99PM62GXP electrical specifications doc id 17639 rev 4 43/102 5.2 esd protection 5.3 thermal data table 9. esd protection parameter value unit all pins (1) 1. hbm (human body model, 100 pf, 1.5 k ) according to mil 883c, method 3015.7 or eia/jesd22a114-a. +/-2 kv all output pins (2) 2. hbm with all none zapped pins grounded. +/-4 kv lin +/-8 (2) +/-10 (3) +/-6 (4) 3. indirect esd test according to iec 61000-4-2 (150 pf, 330 ) and 'hardware requirements for lin, can and flexray interfaces in automotive applications' (version 1.1, 2009-12-02). 4. direct esd test according to iec 61000-4-2 (150 pf, 330 ) and 'hardware requirements for lin, can and flexray interfaces in automotive applications' (version 1.1, 2009-12-02); c bus,lin = 220 pf. kv can_h, can_l +/-8 (2) +/-6 (4) kv all pins (5) 5. charged device model. +/-500 v corner pins (5) +/-750 v all pins (6) 6. machine model: c = 200 pf; r = 0 . +/-200 v table 10. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c r thja thermal resistance junction / ambient see figure 25 k/w table 11. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t w on thermal over temperature warning threshold t j (1) 1. non-overlapping 120 130 140 c t sd1 off thermal shutdown junction temperature 1 t j (1) 130 140 150 c t sd2 off thermal shutdown junction temperature 2 t j (1) 150 160 170 c t sd2 on hysteresis 5 c t sd12hys
electrical specifications L99PM62GXP 44/102 doc id 17639 rev 4 figure 23. thermal data of powersso-36 pad soldered 0 5 10 15 20 25 30 35 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (oc/w) powersso-36 on 2s2p powersso-36 on 2s2p th. enh. pad soldered 0 5 10 15 20 25 30 35 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (oc/w) powersso-36 on 2s2p powersso-36 on 2s2p th. enh. a g00022v1
L99PM62GXP electrical specifications doc id 17639 rev 4 45/102 5.4 package and pcb thermal data 5.4.1 powersso-36 thermal data figure 24. powersso-36 pc board note: layout condition of r th and z th measurements (board finish thickness 1.6 mm +/- 10% board double layer, board dimension 129x60, board material fr4, cu thickness 0.070 mm (front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm). $*9
electrical specifications L99PM62GXP 46/102 doc id 17639 rev 4 figure 25. powersso-36 thermal resistance junction to ambient vs pcb copper area (v1 on) figure 26. powersso-36 thermal impedance junction to ambient vs pcb copper area (single pulse with v1 on) 57+mdpe 57+mdpe 57+mbdpe &: 3&%&xkhdwvlqnduhdfpa $*9 100 zth (c/w) cu=8 cm2 cu=2 cm 2 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 0.01 0.1 1 10 100 1000 zth (c/w) time ( s ) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 0.01 0.1 1 10 100 1000 zth (c/w) time (s) cu=8 cm2 cu=2 cm2 cu=foot print a g00025v1
L99PM62GXP electrical specifications doc id 17639 rev 4 47/102 figure 27. powersso-36 thermal fitting model (v1 on) equation 1: pulse calculation formula table 12. thermal parameter area/island (cm 2 ) footprint 2 8 r1 (c/w) 2 r2 (c/w) 8 4 4 r3 (c/w) 20 15.5 10 r4 (c/w) 36 29 18 c1 (w.s/c) 0.01 c2 (w.s/c) 0.1 0.2 0.2 c3 (w.s/c) 0.8 1 1.5 c4 (w.s/c) 2 3 6 $*9 z th r th z thtp 1 ? () + ? = where t p t ? =
electrical specifications L99PM62GXP 48/102 doc id 17639 rev 4 5.5 electrical characteristics 5.5.1 supply and supply monitoring the voltages are referred to ground and currents are assumed positive, when the current flows into the pin t j = -40 c to 130 c, unless otherwise specified. table 13. supply and supply monitoring symbol parameter test condition min. typ. max. unit v suv v s undervoltage threshold v s increasing / decreasing 5.11 5.81 v v hyst_uv v s undervoltage hysteresis 0.0 0.1 0.15 v v sov v s overvoltage threshold v s increasing / decreasing 18.5 22 v v hyst_ov v s overvoltage hysteresis hysteresis 0.5 1 1.5 v t ovuv_filt v s over/undervoltage filter time 64*t osc i v(act) current consumption in active mode vs = 12v txd can = high txd lin = high v 1 = on, v 2 = on hs/ls driver off 612ma i v(bat) current consumption in v bat standby mode v s = 12v both voltage regulators deactivated, no wake-up request (1) hs/ls driver off 81228a i v(bat)cs current consumption in v bat standby mode with cyclic sense enabled v s = 12v both voltage regulators deactivated, t = 50 ms, ton = 100 s no wake-up request (1) 70 110 130 a i v(bat)cw current consumption in v bat standby mode with cyclic wake enabled v s = 12v both voltage regulators deactivated during standby phase no wake-up request (1) 70 110 130 a i (v1) current consumption in v 1 -standby mode v s = 12v voltage regulator v 1 active, (i v1 < i cmp ) no wake-up request (1) hs/ls driver off 16 51 76 a 1. conditions for no wake-up request are (all conditions must be met): 2 v < lin < (v s -2 v) 0.4 v < (can_h ? can_l) < 1,2 v 1v < v wuth < (v s -2 v) the current consumption in standby modes with cyclic sense can be calculated using the following formulas: i v(bat)cs = i v(bat) + 55 a + (2 ma * (t on + 100 s) / t) i (v1)cs = i v1 + 55 a + (2 ma * (t on + 100 s) / t)
L99PM62GXP electrical specifications doc id 17639 rev 4 49/102 5.5.2 oscillator the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. 5.5.3 power-on reset (v s ) all outputs open; t j = -40c to 130c, unless otherwise specified. 5.5.4 voltage regulator v 1 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; t j = -40 c to 130 c, unless otherwise specified. table 14. oscillator symbol parameter test condition min. typ. max. unit f clk oscillation frequency 0.80 1.0 1.35 mhz table 15. power-on reset (v s ) symbol parameter test condition min. typ. max. unit v por v por threshold vs increasing 3.45 4.5 v v por v por threshold vs decreasing (1) 1. this threshold is valid if vs had already reached 7v previously 2.65 3.5 v table 16. voltage regulator v 1 symbol parameter test condition min. typ. max. unit v 1 output voltage 5.0 v v 1 output voltage tolerance active mode i load1 = 4 ma to 100 ma; v s = 13.5 v -2 +2 % v hc1 output voltage tolerance active mode, high current i load1 = 100 ma to 250 ma; v s = 13.5 v -3 +3 % i load1 = 250 ma; v s = 13.5 v -5 +5 % v stb1 output voltage tolerance v 1 -standby mode i load1 = 0 a to 4 ma; v s = 13.5 v -2 +4 % v dp1 drop-out voltage i load1 = 50 ma; v s = 5 v 0.2 0.4 v i load1 = 100 ma; v s = 4.5 v 0.2 0.5 v i load1 = 100 ma; v s = 5 v 0.3 0.5 v i load1 = 150 ma; v s = 4.5 v 0.45 0.6 v i load1 = 150 ma; v s = 5.0 v 0.45 0.6 v i cc1 output current in active mode max. continuous load current 250 ma i ccmax1 short circuit output current current limitation 340 600 900 ma
electrical specifications L99PM62GXP 50/102 doc id 17639 rev 4 5.5.5 voltage regulator v 2 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; t j = -40 c to 130 c, unless otherwise specified. c load1 load capacitor1 ceramic (+/- 20%) 0.22 (1) f t tsd v 1 deactivation time after thermal shutdown 1sec i cmp_ris current comp. rising thresh. rising current 1.0 2.5 4 ma i cmp_fal current comp. falling threshold falling current 0.8 1.95 3.1 ma i cmp_hys current comp. hysteresis 0.5 ma v 1fail v 1 fail threshold v 1 forced 2 v tv 1fail v 1 fail filter time 2 s tv 1short v 1 short filter time 4 ms 1. nominal capacitor value required for stability of the regulat or. tested with 220 nf ceramic (+/- 20 %). capacitor must be located close to the regulator output pin. table 16. voltage regulator v 1 (continued) symbol parameter test condition min. typ. max. unit table 17. voltage regulator v 2 symbol parameter test condition min. typ. max. unit v 2 output voltage 5,0 v v 2 output voltage tolerance active mode i load2 = 1 ma to 50 ma; v s = 13.5 v +/- 3 % v hc1 output voltage tolerance active mode i load2 = 50 ma to 80 ma; v s = 13,5 v +/- 4 % v 2 output voltage tolerance active mode, high current i load2 = 100 ma; v s = 13.5 v +/- 6 % v stb2 output voltage tolerance v 1 standby mode i load2 = 1 ma; v s = 13.5 v +/-6.5 % v dp2 drop-out voltage i load2 = 25 ma; v s = 5.25 v 0.3 0.4 v i load2 = 50 ma; v s = 5.25 v 0.4 0.7 v i cc2 output current in active mode max. continuous load current 100 ma i ccmax2 short circuit output current current limitation 150 280 450 ma c load load capacitor ceramic (+/- 20 %) 0.22 (1) f v 2fail v 2 fail threshold v 2 forced 2 v t v2fail v 2 fail filter time 2 s t v2short v 2 short filter time 4 ms 1. nominal capacitor value required for stability of the regulat or. tested with 220 nf ceramic (+/- 20 %). capacitor must be located close to the regulator output pin.
L99PM62GXP electrical specifications doc id 17639 rev 4 51/102 5.5.6 reset output the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 4.0 v < v s = 28 v; t j = -40 c to 130 c, unless otherwise specified. 5.5.7 watchdog 4.5 v < v s < 28 v; 4.8 v < v 1 < 5.2 v; t j = -40 c to 130 c, unless otherwise specified, see figure 28 and figure 29 . table 18. reset output symbol parameter test condition min. typ. max. unit v rt1 reset threshold voltage1 v 1 decreasing 3.7 3.9 4.1 v v rt2 reset threshold voltage2 v 1 decreasing 4.2 4.3 4.45 v v rt3 reset threshold voltage3 v 1 decreasing 4.25 4.4 4.55 v v rt4 reset threshold voltage4 v1 decreasing 4.5 4.60 4.75 v vrt4 reset threshold voltage4 v 1 increasing 4.7 4.8 4.9 v v reset reset pin low output voltage v 1 > 1 v; i reset =5ma 0,2 0,4 v r reset reset pull up int. resistor 80 110 150 k t rr reset reaction time i load1 = 1 ma 6 40 s t uv1 v 1 under-voltage filter time 16 s trd reset pulse duration 1.46 2 2.5 ms table 19. watchdog symbol parameter test condition min. typ. max. unit t lw long open window 48,75 65 81,25 ms t efw1 early failure window 1 4.5 ms t lfw1 late failure window 1 20 ms t sw1 safe window 1 7.5 12 ms t efw2 early failure window 2 22.3 ms t lfw2 late failure window 2 100 ms t sw2 safe window 2 37.5 60 ms t efw3 early failure window 3 45 ms t lfw3 late failure window 3 200 ms t sw3 safe window 3 75 120 ms t efw4 early failure window 4 90 ms t lfw4 late failure window 4 400 ms t sw4 safe window 4 150 240 ms
electrical specifications L99PM62GXP 52/102 doc id 17639 rev 4 figure 28. watchdog timing (long, early, late and safe window) 7 /: orqjzlqgrz 7 &: forvhgzlqgrz 7 2: rshqzlqgrz wuljjhuvljqdo 7 :'5 zdwfkgrjuhvhw wlphpv wlphpv wlphpv 1rupdovwduwxsrshudwlrqdqgwlphrxwidloxuhv :' wuljjhu fruuhfwwuljjhuwlplqj 7 /: 7 &: 7 2: 0lvvlqjx&wuljjhuvljqdo 7 &: 7 &: 7 2: 15(6 2xw 7 :'5 7 /: hduo\wuljjhuwlplqj plvvlqjwuljjhu 7 /: 7 :'5 qrupdorshudwlrq plvvlqj wuljjhu hduo\ zulwh 7 /: 15(6 2xw 7 :'5 7 :'5 :' wuljjhu 7 /: 7 /: 7 :'5 wlphpv $*9
L99PM62GXP electrical specifications doc id 17639 rev 4 53/102 figure 29. watchdog early, late and safe windows 5.5.8 high-side outputs the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t j = -40 c to 130 c, unless otherwise specified. vdihwuljjhuduhd 7():qbpd[ 76:qbplq 7/):qbplq 76:q 6dihzlqgrz 7():q (duo\)dloxuhzlqgrz 7/):q /dwhidloxuhzlqgrz wlph (duo\ :dwfkgrj idloxuh xqghilqhg xqghilqhg 76:qbpd[ /dwh zdwfkgrj idloxuh $*9 table 20. output (out_hs) symbol parameter test condition min. typ. max. unit r ds on static drain source on-resistance (iout_hs = 150 ma) t j = 25 c 1 2 t j = 125 c 1.6 3 t d on switch on delay time 0.2 v s 53560s t d off switch off delay time 0.8 v s 40 95 150 s t scf short circuit filter time tested by scan chain 64*t osc t d arhs auto recovery filter time tested by scan chain 400*t osc dv out /dt slew rate 0,18 0,5 0,8 v/s i out short circuit shutdown current 480 900 1320 ma i old open-load detection current 40 80 120 ma t oldt open-load detection time tested by scan chain 64*t osc i fw (1) 1. parameter guaranteed by design loss of gnd current (esd structure) 100 ma
electrical specifications L99PM62GXP 54/102 doc id 17639 rev 4 the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t j = -40 c to 130 c, unless otherwise specified. 5.5.9 relay drivers the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t j = -40 c to 130 c, unless otherwise specified. table 21. outputs (out1...4) symbol parameter test condition min. typ. max. unit r ds on static drain source on-resistance (iout_hs = 150ma) i load = 60 ma @ t j =+25c 713 i out short circuit shutdown current 8 v < v s < 16 v 140 235 350 ma i old open-load detection current 1 0.9 2 4.5 ma dv out /dt slew rate 0.2 0.5 0.8 v/s t don switch on delay time 0.2 v s 53560s t doff switch off delay time 0.8 v s 30 95 150 s t scf short circuit filter time tested by scan chain 64*t osc i fw (1) 1. parameter guaranteed by design loss of gnd current (esd structure) 100 ma t oldt open-load detection time tested by scan chain 64*t osc table 22. relay drivers symbol parameter test condition min. typ. max. unit r dson dc output resistance i load =100ma @ t j =+25c 2 3 i out short circuit shutdown current 8 v < v s < 16 v 250 375 500 ma v z output clamp voltage (1) i load = 100 ma 40 48 v t onhl turn on delay time to 10% v out 5 50 100 s t offlh turn off delay time to 90% v out 5 50 100 s t scf short circuit filter time tested by scan chain 64*t osc dv out /dt slew rate 0.2 2 4 v/s 1. the output is capable to switch off relay coils with the impedance of rl = 160 ; l = 300mh (rl = 220 ; l = 420mh); at v s = 40v (load dump condition)
L99PM62GXP electrical specifications doc id 17639 rev 4 55/102 5.5.10 wake up inputs ( wu 1... wu 3) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; t j = -40 c to 130 c, unless otherwise specified. 5.5.11 high speed can transceiver (b) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.8 v < vcansup. < 5.2 v; t junction = -40 c to 130 c, unless otherwise specified. table 23. wake up inputs ( wu 1... wu 3) symbol parameter test condition min. typ. max. unit v wuthp wake-up negative edge threshold voltage 0.4*v s 0.45*v s 0.5*v s v v wuthn wake-up positive edge threshold voltage 0.5*v s 0.55*v s 0.6*v s v v hyst hysteresis 0.05*v s 0.1*v s 0.15*v s v t wu_stat static wake filter time 64*t osc s i wu_stdby input current in standby mode 1 v > v in > (v s - 2 v) 9 15 28 a r wu_act input resistor to gnd in active mode and in standby mode during wake-up request 80 160 300 k t wu_cyc cyclic wake filter time 16 (1) s 1. blanking time 80 s or 800 s. b. iso 11898-2 and iso 11898-5 compliant; sae j2284 compliant. table 24. can communication operating range symbol parameter test condition min. typ. max. unit v scom supply voltage operating range for can communication active mode, v 1 = v cansup 5.5 - 18 v table 25. can transmit data input: pin txdc symbol parameter test condition min. typ. max. unit v txdclow input voltage dominant level active mode, v 1 = 5 v 1.35 1.8 v v txdchigh input voltage recessive level active mode, v 1 = 5 v 2.7 2.9 v v txdchys v txdchigh -v txdclow active mode, v 1 = 5 v 0.7 1 v r txdcpu txdc pull up resistor active mode, v 1 = 5 v 10 20 35 k
electrical specifications L99PM62GXP 56/102 doc id 17639 rev 4 table 26. can receive data output: pin rxdc symbol parameter test condition min. typ. max. unit v rxdclow output voltage dominant level active mode, v 1 = 5v, 2ma 0.2 0.5 v v rxdchigh output voltage recessive level active mode, v 1 = 5v, 2ma 4.5 v table 27. can bus common mode stabilization output termination: pin split symbol parameter test condition min. typ. max. unit v split,l split output voltage, loaded condition (normal mode) active mode; v txdc = v txdchigh ; |isplit| = 500 a 0.3* v cansup 0.5* v cansup 0.7* v cansup v v split,u split output voltage, unloaded condition (normal mode) active mode; v txdc = v txdchigh ; no load 0.5* v cansup 0.55* v cansup v i split split leakage current (low power mode) v 1 -standby mode; -12 v < v split <12v 5a table 28. can transmitter and receiver: pins canh and canl symbol parameter test condition min. typ. max. unit v canhdom canh voltage level in dominant state active mode; v txdc =v txdclow ; r l =60 ; r l =50 2.75 4.5 v v canldom canl voltage level in dominant state active mode; v txdc =v txdclow ; r l =60 ; r l =50 0.5 2.25 v v diff,domout differential output voltage in dominant state: v canhdom - v canldom active mode; v txdc =v txdclow ; r l =60 ; r l =50 1.5 3 v v cm driver symmetry: v canhdom +0v canldom active mode; v txdc =v txdclow ; r l =60 ; c split =4.7pf 0.9* v cansup v cansup 1.1* v cansup v v canhrec canh voltage level in recessive state (normal mode) active mode; v txdc =v txdchigh ; no load 22.53v v canlrec canl voltage level in recessive state (normal mode) active mode; v txdc =v txdchigh ; no load 22.53v v canhreclp canh voltage level in recessive state (low power mode) v 1 standby mode; v txdc =v txdchigh ; no load -0.1 0 0.1 v v canlreclp canl voltage level in recessive state (low power mode) v 1 standby mode; v txdc =v txdchigh ; no load -0.1 0 0.1 v
L99PM62GXP electrical specifications doc id 17639 rev 4 57/102 v diff,recout differential output voltage in recessive state (normal mode): v canhrec - v canlrec active mode; v txdc =v txdchigh ; no load -50 50 mv v diff,recoutl p differential output voltage in recessive state (low power mode): v canhrec - v canlrec v 1 standby mode; v txdc =v txdchigh ; no load -50 50 mv v canhl,cm common mode bus voltage measured with respect to the ground of each can node -12 12 v i ocanh,dom canh output current in dominant state active mode; v txdc =v txdclow ; v canh =0v -160 -75 -45 ma i ocanl,dom canl output current in dominant state active mode; v txdc =v txdclow ; v canl =5v 45 75 160 ma i leakage input leakage current unpowered device; v bus =5v 0 250 a r in internal resistance active mode & v 1 standby mode; v txdc =v txdchigh ; no load 20 27.5 38 k r in,matching internal resistor matching canh, canl active mode & v 1 standby mode; v txdc =v txdchigh ; no load r in (canh) - r in (canl) 3% r in,diff differential internal resistance active mode & v 1 standby mode; v txdc =v txdchigh ; no load 50 60 75 k c in internal capacitance guaranteed by design 20 pf c in,diff differential internal capacitance guaranteed by design 10 pf v thdom differential receiver threshold voltage recessive to dominant state (normal mode) active mode 0.9 v v thdomlp differential receiver threshold voltage recessive to dominant state (low power mode) v 1 standby mode 1.15 v v threc differential receiver threshold voltage dominant to recessive state (normal mode) active mode 0.5 v v threclp differential receiver threshold voltage dominant to recessive state (low power mode) v 1 standby mode 0.4 v table 28. can transmitter and rece iver: pins canh and canl (continued) symbol parameter test condition min. typ. max. unit
electrical specifications L99PM62GXP 58/102 doc id 17639 rev 4 5.5.12 lin transceiver (c) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t junction = -40 c to 130 c unless otherwise specified. table 29. can transceiver timing symbol parameter test condition min. typ. max. unit ttxpd,hl propagation delay txdc to rxdc (high to low) active mode; 50 % v txdc to 50 % v rxdc ; c rxdc =100pf; r l =60 0255ns ttxpd,lh propagation delay txdc to rxdc (low to high) active mode; 50 % v txdc to 50 % v rxdc ; c rxdc =100pf; r l =60 0255ns t wake wake up filter time 0.5 5 s t dom(txdc) txdc dominant time-out 700 s t can can permanent dominant time-out 700 s c. lin 2.1 compliant for baud rates up to 20 kbit/s sae j2602 compatible table 30. lin transmit data input: pin txd symbol parameter test condition min. typ. max. unit v txdlow input voltage dominant level active mode; v 1 = 5 v 1,35 1.8 v v txdhigh input voltage recessive level active mode; v 1 =5v 2.7 2.9 v v txdhys v txdhigh -v txdlow active mode; v 1 =5v 0.7 1 v r txdpu txd pull up resistor active mode; v 1 =5v 10 20 35 k table 31. lin receive data output: pin rxd symbol parameter test condition min. typ. max. unit v rxdlow output voltage dominant level active mode; v 1 =5v, i load1 = 2 ma 0.2 0.5 v v rxdhigh output voltage recessive level active mode; v 1 =5v, i load1 = 2 ma 4.5 v table 32. lin transmitter and receiver: pin lin symbol parameter test condition min. typ. max. unit v thdom receiver threshold voltage recessive to dominant state 0.4*v s 0.45*v s 0.5*v s v v busdom receiver dominant state 0.4*v s v
L99PM62GXP electrical specifications doc id 17639 rev 4 59/102 v threc receiver threshold voltage dominant to recessive state 0.5*v s 0.55*v s 0.6*v s v v busrec receiver recessive state 0.6*v s v v thhys receiver threshold hysteresis: v threc -v thdom 0.07*v s 0.1*v s 0.175*v s v v thcnt receiver tolerance center value: (v threc +v thdom )/2 0.475*v s 0.5*v s 0.525*v s v v thwkup receiver wakeup threshold voltage 1.0 1.5 2 v v thwkdwn receiver wakeup threshold voltage v s -3.5 v s -2.5 v s -1.5 v t linbus dominant time for wakeup via bus sleep mode; edge: rec-dom 64*t osc s i lindomsc transmitter input current limit in dominant state v txd =v txdlow ; v lin =v batmax =18v 40 100 180 ma i bus_pas_dom input leakage current at the receiver incl. pull-up resistor v txd =v txdhigh ; v lin =0v; v bat =12v (1) -1 ma i bus_pas_rec transmitter input current in recessive state v txd =v txdhigh ; 8v= v bat in standby modes 20 a i bus_no_gnd input current if loss of gnd at device gnd = v s ; 0v electrical specifications L99PM62GXP 60/102 doc id 17639 rev 4 table 33. lin transceiver timing symbol parameter test condition min. typ. max. unit t rxpd receiver propagation delay time t rxpd =max(t rxpdr , t rxpdf ); t rxpdf =t(0.5v rxd )-t(0.45v lin ); t rxpdr =t(0.5v rxd ) - t(0.55 v lin ); v s =12v; c rxd =20pf; r bus , = 1 k , c bus = 1 nf; r bus = 660 , c bus = 6.8 nf; r bus = 500 , c bus = 10 nf 6s t rxpd_sym symmetry of receiver propagation delay time (rising vs. falling edge) t rxpd_sym =t rxpdr - t rxpdf ; v s =12v; r bus =1k , c bus =1nf -2 2 s d1 duty cycle 1 th rec (max) = 0.744*v s ; th dom (max) = 0.581*v s ; v s = 7 v to 18 v, t bit =50 s; d1 = t bus_rec (min)/(2xt bit ); r bus =1k , c bus =1nf; r bus = 660 , c bus =6.8nf; r bus = 500 , c bus =10nf 0.396 d2 duty cycle 2 th rec (min) = 0.284*v s ; th dom (min) = 0.422*v s ; v s = 7.6 to 18 v, t bit = 50 s; d2 = t bus_rec (max)/(2xt bit ); r bus =1k , c bus =1nf; r bus = 660 , c bus =6.8nf; r bus = 500 , c bus =10nf 0.581 d3 duty cycle 3 th rec (max) = 0.778*v s ; th dom (max) = 0.616*v s; v s = 7 v to 18 v, t bit = 96 s; d3 = t bus_rec (min)/(2xt bit ); r bus =1k , c bus =1nf; r bus = 660 , c bus =6.8nf; r bus = 500 , c bus =10nf 0.417 d4 duty cycle 4 th rec (min) = 0.251*v s ; th dom (min) = 0.389*v s ; v s = 7.6 v to 18 v, t bit = 96 s; d4 = t bus_rec (max)/(2xt bit ); r bus =1k , c bus =1nf; r bus = 660 , c bus =6.8nf; r bus = 500 , c bus =10nf 0.590 t dom(txdl) txdl dominant time-out 12 ms t lin lin permanent recessive time-out 40 s t dom(bus) lin bus permanent dominant time-out 12 ms
L99PM62GXP electrical specifications doc id 17639 rev 4 61/102 figure 30. lin transmit, receive timing 5.5.13 operational amplifier the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; t j = -40 c to 130 c, unless otherwise specified. table 34. lin pull-up: pin linpu symbol parameter test condition min. typ. max. unit rds on on resistance 10.5 16 i leak leakage current 1 a wlph wlph 9 7[' 9 /,1 9 7+uhf 9 7+grp wlph 9 5[' 9 /,1grp 9 /,1uhf w 7;sgi w 7;sgu w 5;sgi w 5;sgu $*9 table 35. operational amplifier symbol parameter test condition min. typ. max. unit gbw gbw product 1 3.5 7.0 mhz avol dc dc open loop gain 80 db psrr power supply rejection dc, vin = 150 mv 80 db v off input offset voltage -5 +5 mv v icr common mode input range -0.2 0 3 v v oh output voltage range high i load = 1 ma to gnd v s -0.2 v s v v ol output voltage range low i load = 1 ma to v s 0 0.2 v i lim+ output current limitation + dc 10 15 30 ma i lim- output current limitation - dc -10 15 -30 ma
electrical specifications L99PM62GXP 62/102 doc id 17639 rev 4 note: the operational amplifier is on-chip stabilized for external capacitive loads c l < 25 pf (all operating conditions) 5.5.14 spi input: csn the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. input: csn clk, di the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. sr+ slew rate positive 1 4 10 v/s sr- slew rate negative -1 -4 -10 v/s table 35. operational amplifier (continued) symbol parameter test condition min. typ. max. unit table 36. input: csn symbol parameter test condition min. typ. max. unit vcsnlow input voltage low level normal mode, v 1 = 5 v 1.35 1.8 v vcsnhigh input voltage high level normal mode, v 1 =5v 2.7 2.9 v vcsnhys vcsnhigh - vcsnlow normal mode, v 1 =5v 0.6 1.0 1.5 v icsnpu csn pull up resistor normal mode, v 1 =5v 10 20 35 k table 37. input clk, di symbol parameter test condition min. typ. max. unit t set delay time from standby to active mode switching from standby to active mode. time until output drivers are enabled after csn going to high. 160 300 s v in l input low level v 1 = 5 v 1.0 2.05 2.5 v v in h input high level v 1 = 5 v 1.5 2.8 3.5 v v in hyst input hysteresis v 1 = 5 v 0.4 0.75 1.5 v i in pull down current at input v in = 1.5 v 5 30 60 a
L99PM62GXP electrical specifications doc id 17639 rev 4 63/102 di timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. do the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. c in (1) input capacitance at input csn, clk, di and pwm 1,2 0v < v 1 < 5.3 v 10 15 pf f clk spi input frequency at clk 1mhz 1. value of input capacity is not measured in production test. parameter guaranteed by design. table 38. di timing (1) 1. see figure 32 . symbol parameter test condition min. typ. max. unit t clk clock period v 1 = 5 v 1000 - ns t clkh clock high time v 1 = 5 v 400 - ns t clkl clock low time v 1 = 5 v 400 - ns t set csn csn setup time, csn low before rising edge of clk v 1 = 5 v 400 - ns t set clk clk setup time, clk high before rising edge of csn v 1 = 5 v 400 - ns t set di di setup time v 1 = 5 v 200 - ns t hold di di hold time v 1 = 5 v 200 - ns t r in rise time of input signal di, clk, csn v 1 = 5 v - 100 ns t f in fall time of input signal di, clk, csn v 1 = 5 v - 100 ns table 39. do output pin symbol parameter test condition min. typ. max. unit v dol output low level v 1 = 5 v, i d = -4 ma 0.5 v v doh output high level v = 5 v, i d = 4 ma 4.5 v table 37. input clk, di (continued) symbol parameter test condition min. typ. max. unit
electrical specifications L99PM62GXP 64/102 doc id 17639 rev 4 do timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. csn timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. i dolk 3-state leakage current v csn = v 1 , 0 v < v do < v 1 -10 10 a c do 2 3-state input capacitance v csn = v 1 , 0 v < v 1 < 5.3 v 10 15 pf table 40. do timing (1) 1. see figure 33 and figure 34 . symbol parameter test condition min. typ. max. unit t r do do rise time c l = 100 pf, i load = -1 ma - 50 100 ns t f do do fall time c l = 100 pf, i load = 1 ma - 50 100 ns t en do tri l do enable time from 3-state to low level c l = 100 pf, i load = 1 ma pull-up load to v 1 -50250ns t dis do l tri do disable time from low level to 3-state c l = 100 pf, i load = 4 ma pull-up load to v 1 -50250ns t en do tri h do enable time from 3-state to high level c l = 100 pf, i load = -1 ma pull-down load to gnd -50250ns t dis do h tri do disable time from high level to 3-state c l = 100 pf, i load = -4 ma pull-down load to gnd -50250ns t d do do delay time v do < 0.3 v 1 , v do > 0.7 v 1 , c l = 100 pf -50250ns table 41. csn timing (1) 1. see figure 35 . symbol parameter test condition min. typ. max. unit tcsn_hi,min minimum csn hi time, active mode transfer of spi-command to input register 6s t csnfail csn low timeout tested by scan chain 20 35 50 ms table 39. do output pin (continued) symbol parameter test condition min. typ. max. unit
L99PM62GXP electrical specifications doc id 17639 rev 4 65/102 rxdl/nint timing the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v < v s < 18 v; 4.5 v < v 1 < 5.3 v; all outputs open; t j = -40 c to 130 c, unless otherwise specified. 5.5.15 inputs txd_c and txd_l for flash mode 6v vs 18 v; 4.5 v v 1 5.3 v; t j = -40 c to 130 c, voltages are referred to pgnd, all outputs open figure 31. spi ? transfer timing diagram table 42. rxdl/nint timing symbol parameter test condition min. typ. max. unit t interupt interrupt pulse duration walk-up from v 1-standby ?56 ?s table 43. inputs txd_c and txd_l for flash mode symbol parameter test condition min. typ. max. unit v flashl input low level (v txdc/l for transition into flash mode) v 1 = 5v 6.17.258.4 v v flashh input high level (v txdc/l for exit from flash mode) v 1 = 5 v 7.4 8.4 9.4 v v flashhys input voltage hysteresis v 1 = 5 v 0.6 0.8 1.0 v &61 &/. ', '2 ,qsxw 'dwd 5hjlvwhu &61kljkwrorz'2hqdeohg wlph ',gdwdzlooehdffhswhgrqwkhulvlqjhgjhri&/.vljqdo wlph wlph wlph wlph '2gdwdzloofkdqjhrqwkhidoolqjhgjhri&/.vljqdo *oredo(uuru &61orzwrkljkdfwxdogdwdlv wudqvihuhgwrrxwsxwsrzhuvzlwfkhv roggdwd qhzgdwd ; ; ; ; ; ; &rppdqg%\wh *oredo6wdwxv%\wh 'dwd $*9
electrical specifications L99PM62GXP 66/102 doc id 17639 rev 4 the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. figure 32. spi - input timing 9&& 9&& 9&& 9&& 9&& 9&& 9do l g 9dol g &61 &/. ', w vhw &61 w &/.+ w vhw &/. w &/./ w kro g ', w vhw ', $*9
L99PM62GXP electrical specifications doc id 17639 rev 4 67/102 figure 33. spi output timing (part 1) 7i &/. 7u &/. &/. 9ff 9ff 9ff '2 orzwrkljk 9ff 9ff 7u '2 7g '2 9ff 9ff 7i '2 '2 kljkwrorz 7i &61 7u &61 &61 9ff 9ff 9ff 7h q '2bwulb/ 7h q '2bwulb+ 7glv '2b/bwul 7glv '2b+bwul $*9
electrical specifications L99PM62GXP 68/102 doc id 17639 rev 4 figure 34. spi output timing (part 2) figure 35. spi ? csn low to high transition and global status bit access &61 g21 w w ulq ilq w 2)) w g2)) w 2)) vwdwh 21 vwdwh 2)) vwdwh 21 vwdwh 21 w rxwsxw fxuuhqw ri d gulyhu rxwsxw fxuuhqw ri d gulyhu &61 orz wr kljk gdwd iurp vkliw uhjlvwhu lv wudqvihuuhg wr rxwsxw srzhu vzlwfkhv w &61b+,plq $*9 &61 &/. ', '2 &61 kljk wr orz dqg &/. vwd\v orz vwdwxv lqirupdwlrq ri gdwd elw idxow frq glwlrq lv wudqvihuhg wr '2 ', gdwd lv qrw dffhswhg '2 vwdwxv lqirupdwlrq ri gdwd elw idxow frqglwlrq zloo vwd\ dv orqj dv & 61 lv orz wlph wlph wlph wlph $*9
L99PM62GXP st spi doc id 17639 rev 4 69/102 6 st spi 6.1 spi communication flow 6.1.1 general description the proposed spi communication is based on a standard spi interface structure using csn (chip select not), sdi (serial data in), sdo (serial data out/error) and sck (serial clock) signal lines. at device start-up the master reads the register (rom address 3eh) of the slave device. this 8-bit register indicates the spi frame length (24bit) and the availability of additional features. each communication frame consists of an instruction byte which is followed by 2 data bytes. the data returned on sdo within the same frame always starts with the register. it provides general status information about the device. it is followed by 2 data bytes (i. e. ?in-frame-response?). for write cycles the register is followed by the previous content of the addressed register. for read cycles the register is followed by the content of the addressed register. a write command is only accepted as a valid command by the device if the counted number of clocks is exact 24, otherwise the command is rejected. command byte each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation (, , , ) and a 6 bit address. if less than 6 address bits are required, the remaining bits are unused but are reserved. ocx: operating code ax: address 6.1.2 operating code definition table 44. command byte msb lsb op code address oc1 oc0 a5 a4 a3 a2 a1 a0 table 45. operating code definition oc1 oc0 meaning 0 0 0 1
st spi L99PM62GXP 70/102 doc id 17639 rev 4 the and operations allow access to the ram of the device, i. e. to write to control registers or read status information. a operation addressed to a device specific status register reads back and subsequently clear this status register. a operation with address 3fh clears all status registers (including the global status register). configuration register is read by this operation. allows access to the rom area which contains device related information such as the product family, product name, silicon version, register width and availability of a watchdog. more detailed descriptions of the device information are available in ?read device information?. 6.1.3 global status register (d) 6.1.4 configuration register the register is accessible at ram address 3fh. for the config register, the 8 bits are located in the low byte (lsb). the configuration register is implemented for compliance purpose to st spi standard. : this bit is reserved to serve the watchdog. 1 0 1 1 table 45. operating code definition (continued) oc1 oc0 meaning d. see section 6.2 for details. table 46. global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global error flag (gef) comm error not (chip reset or comm error) tsd2 tsd1 v 1 fail vs fail (ov/uv) fail safe table 47. configuration register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000000 wd trigger
L99PM62GXP st spi doc id 17639 rev 4 71/102 figure 36. read configuration register (1) 1. the configuration register is implemented for comp liance with st standard spi 3.0 and contains only the watchdog trigger bit at d0 figure 37. write configuration register (1) 1. the configuration register is implemented for comp liance with st standard spi 3.0 and contains only the watchdog trigger bit at d0 &61 6', &rppdqg )dlo 6dih 9v )dlo 9 )dlo 76' 76' 127 &kls 5hv 25 &rpp (uu &rp (uuru *() 6'2 *oredo6wdwxv 75,* $*9 &61 6', &rppdqg )dlo 6dih 9v )dlo 9 )dlo 76' 76' 127 &kls 5hv 25 &rpp (uu &rp (uuru *() 6'2 *oredo6wdwxv 75,* q 75,* q $*9
st spi L99PM62GXP 72/102 doc id 17639 rev 4 6.1.5 address mapping the ram memory area consists of 16 bit registers. for the device information (rom memory area) the eight most significant bits of the memory cell are used. the remaining 8 are zero. all unused ram and rom addresses is read as ?0?. note: 1 the register definition for ram address 00h is unused. a register value of all 0 must cause the device to enter a fail-safe state (interpreted as ?sdi stuck to gnd? failure). 2 rom address 3fh is unused. an attempt to access this address must be recognized as a communication error (?sdi stuck to v cc ? failure) and must cause the device to enter a fail- safe state. 6.1.6 write operation the write operation starts with a command byte followed by 2, data bytes. the number of data bytes is specified in the . write command format table 48. address mapping ram adress description access rom adress description access 3fh r/w 3fh reserved n/a 13h status register 3 r 3eh r 12h status register 2 r 11h status register 1 r ? unused n/a 06h control register 6 r/w 03h n/a 05h control register 5 r/w 04h control register 4 r/w 02h r 03h control register 3 r/w 02h control register 2 r/w 01h r 01h control register 1 r/w 00h reserved r/w 00h r table 49. write command format: command byte msb lsb op code address 0 0 a5 a4 a3 a2 a1 a0
L99PM62GXP st spi doc id 17639 rev 4 73/102 oc0, oc1:operating code (00 for ?write? mode) a0 to a5:address bits an attempt to write 00h at ram address 00h is recognized as a failure (sdi stuck to gnd). the device enters a fail-safe state. 6.1.7 format of data shifted out at sdo during write cycle failures are indicated by activating the corresponding bit of the register. the returned data byte(s) represent(s) the previous content of the accessed register. table 50. write command format: data byte 1 msb lsb d15 d14 d13 d12 d11 d10 d9 d8 table 51. write command format: data byte 2 msb lsb d7 d6 d5 d4 d3 d2 d1 d0 table 52. format of data shifted out at sdo during write cycle: global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global error flag (gef) comm error not (chip reset or comm error) tsd2 tsd1 v 1 fail v s fail (ov/uv) fail safe table 53. format of data shifted out at sdo during write cycle: data byte 1 msb previous content of addressed register lsb d15 d14 d13 d12 d11 d10 d9 d8 table 54. format of data shifted out at sdo during write cycle: data byte 2 msb previous content of addressed register lsb d7 d6 d5 d4 d3 d2 d1 d0
st spi L99PM62GXP 74/102 doc id 17639 rev 4 figure 38. format of data shifted out at sdo during write cycle 6.1.8 read operation the read operation starts with a command byte followed by 2 data bytes. the number of data bytes is specified in the . the content of the data bytes is ?don?t care?. the content of the addressed register is shifted out at sdo within the same frame (?in-frame response?). read command format oc0, oc1:operating code (01 for ?read? mode) $ $ $ $ $ $ &61 6', &rppdqg ' ' ' ' ' ' ' ' )dlo 6dih 9v )dlo 9 )dlo 76' 76' 127 &kls 5hv 25 &rpp (uu &rp (uuru *() 6'2 *oredo6wdwxv vw 'dwde\wh suhylrxvfrqwhqwriuhjlvwhu ' ' ' ' ' ' ' ' qg 'dwde\wh suhylrxvfrqwhqwriuhjlvwhu ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' vw 'dwde\wh qg 'dwde\wh $*9 table 55. read command format: command byte msb lsb op code address 0 1 a5 a4 a3 a2 a1 a0 table 56. read command format: data byte 1 msb lsb 00000000 table 57. read command format: data byte 2 msb lsb 00000000
L99PM62GXP st spi doc id 17639 rev 4 75/102 a0 to a5:address bits 6.1.9 format of data shifted out at sdo during read cycle failures are indicated by activating the corresponding bit of the register. the returned data byte(s) represent(s) the content of the register to be read. figure 39. format of data shifted out at sdo during read cycle table 58. format of data shifted out at sdo during read cycle: global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global error flag (gef) comm error not (chip reset or comm error) tsd2 tsd1 v 1 fail v s fail (ov/uv) fail safe table 59. format of data shifted out at sdo during read cycle: data byte 1 msb previous content of addressed register lsb d15 d14 d13 d12 d11 d10 d9 d8 table 60. format of data shifted out at sdo during read cycle: data byte 2 msb previous content of addressed register lsb d7 d6 d5 d4 d3 d2 d1 d0 $ $ $ $ $ $ &61 6', &rppdqg ' ' ' ' ' ' ' ' )dlo 6dih 9v )dlo 9 )dlo 76' 76' 127 &kls 5hv 25 &rpp (uu &rp (uuru *() 6'2 *oredo6wdwxv vw 'dwde\wh ' ' ' ' ' ' ' ' qg 'dwde\wh $*9
st spi L99PM62GXP 76/102 doc id 17639 rev 4 6.1.10 read and clear status operation the ?read and clear status? operation starts with a command byte followed 2 data bytes. the number of data bytes is specified in the . the content of the data bytes is ?don?t care?. the content of the addressed status register is transferred to sdo within the same frame (?in-frame response?) and is subsequently cleared. a ?read and clear status? operation with address 3fh clears all status registers (incl. the register). the configuration register is read by this operation. read and clear status command format oc0, oc1:operating code (10 for ?read and clear status? mode) a0 to a5:address bits format of data shifted out at sdo during read and clear status operation table 61. read and clear status command format: command byte msb lsb op code address 1 01a5a4a3a2a1a0 table 62. read and clear status command format: data byte 1 msb lsb 00000000 table 63. read and clear status command format: data byte 2 msb lsb 00000000 table 64. format of data shifted out at sdo during read and clear status: global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global error flag (gef) comm error not (chip reset or comm error) tsd2 tsd1 v 1 fail v s fail (ov/uv) fail safe table 65. format of data shifted out at sdo during read and clear status: data byte 1 msb previous content of addressed register lsb d15 d14 d13 d12 d11 d10 d9 d8
L99PM62GXP st spi doc id 17639 rev 4 77/102 failures are indicated by activating the corresponding bit of the register. the returned data byte(s) represent(s) the content of the register to be read. figure 40. format of data shifted out at sdo during read and clear status operation 6.1.11 read device information the device information is stored at the rom addresses defined below and is read using the respective operating code. table 66. format of data shifted out at sdo during read and clear status: data byte 2 msb previous content of addressed register lsb d7 d6 d5 d4 d3 d2 d1 d0 $ $ $ $ $ $ &61 6', &rppdqg ' ' ' ' ' ' ' ' )dlo 6dih 9v )dlo 9 )dlo 76' 76' 127 &kls 5hv 25 &rpp (uu &rp (uuru *() 6'2 *oredo6wdwxv vw 'dwde\wh &rqwhqwridgguhvvhg6wdwxv5hjlvwhu ' ' ' ' ' ' ' ' qg 'dwde\wh &rqwhqwridgguhvvhg6wdwxv5hjlvwhu $*9 table 67. read device information op code rom address device information value oc1 oc0 1 1 3fh reserved 00 11 3eh includes frame width and availability of watchdog 42 hex 1 1 04h to 3dh unused 00 11 03h unique product identifier 4b hex
st spi L99PM62GXP 78/102 doc id 17639 rev 4 the (rom address 00h) indicates the product family and specifies the highest address which contains product information : 01 hex (bcd) :03 hex the ( rom address 02h) and < product code 2> ( rom address 03h) represents a unique code to identify the product name. 13 hex 4b hex the (rom address 01h) provides information about the silicon version according to the table below: 11 02h unique product identifier 13 hex 11 01h indicates design version according to silicon version 11 00h device family max adress of device information 43 hex table 68. id-header bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01000011 family identifier highest address containing device information table 69. family identifier bit 7 bit 6 meaning 0 0 vipower 0 1 bcd 1 0 vipower hybrid 11 tbd table 70. silicon version identifier bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved silicon version table 67. read device information (continued) op code rom address device information value oc1 oc0
L99PM62GXP st spi doc id 17639 rev 4 79/102 the (rom address 3eh) provides information about the register width (1, 2, 3 bytes) and the availability of ?burst mode read? and watchdog. br:burst-mode read (1 = burst-mode read is supported) wd:watchdog (1 = available, 0 = not available) 32-bit, 24-bit, 16-bit: width of spi frame (see table below) :not supported :available :24 bit 6.2 spi registers 6.2.1 overview overview command byte table 71. spi-frame-id bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01000 0 1 0 br wd x x x 32-bit 24-bit 16-bit table 72. spi register: command byte read/write address xxxxxxxx table 73. spi register: mode selection read/write mode selection 00 write 01 read 1 0 read and clear 1 1 read device info table 74. spi register: ctrl register selection ctrl register 1?6 ctrl register selection 000001 ctrl register1 000010 ctrl register2 000011 ctrl register3 000100 ctrl register4
st spi L99PM62GXP 80/102 doc id 17639 rev 4 overview of control register data bytes 000101 ctrl register5 000110 ctrl register6 table 75. spi register: stat register selection stat register. 1?3 stat register selection 010001 stat register1 010010 stat register2 010011 stat register3 table 74. spi register: ctrl register selection (continued) ctrl register 1?6 ctrl register selection
L99PM62GXP st spi doc id 17639 rev 4 81/102 6.2.2 control registers table 76. overview of control registers data bytes 1 st data byte <15:8> 2 nd data byte <7:0> control register 1, data defaults0000 0 0 0000 0 0 0 0 0 function out hs out hs out 4 out 4 out hs_ext out 3 out 2 out 1 rel 2 rel 1 v 2 v 2 res stby sel go stby trig group hs control ls output, v 2 and mode control control register 2, data defaults 0 0 0 0 0 0 0 0 0 0 1 1 1 function res res inp. filt 3 inp. filt 3 inp. filt 2 inp. filt 2 inp. filt 1 inp. filt1 res input pu/pd 3 input pu/pd 2 input pu/pd 1 res wu en 3 wu en 2 wu en 1 group wake-up control wake-up control control register 3, data defaults 0 0 0 0 0 0 0 0 1 1 0 0 function res t1 on t1 per t1 per res t2 on t2 per t2 per res res wd time wd time lin wu en can wu en wake timer en wake timer select group timer settings watchdog and cyclic wake up settings control register 4, data defaults 0 0 1 1 0 0 1 1 1 1 0 1 1 0 function res i cmp ouths rec en vlock out en res ls ov/uv shut down_en v 1 reset level v 1 reset level lin pu en res lin txd to u t en can act can loop en can patt. wake en can split on can rec only group control (other) transceiver settings control register 5, data defaults 111 1 1 1100 0 0 0 0 0 0 function res pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm freq pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc group pwm2 setting pwm1 setting control register 6, data defaults 111 1 1 11 0 0 0 0 0 0 0 function res pwm4 off-dc pwm4 off-dc pwm4 off-dc pwm4 off- dc pwm4 off- dc pwm4 off-dc pwm4 off-dc res pwm3 on- dc pwm3 on- dc pwm3 on- dc pwm3 on- dc pwm3 on- dc pwm3 on- dc pwm3 on- dc group pwm4 setting pwm3 setting
st spi L99PM62GXP 82/102 doc id 17639 rev 4 control register 1 table 77. control register 1: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 0 0 1 data, 8bit data, 8 bit table 78. control register 1, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 function out hs_2 out hs_1 out 4_2 out 4_1 out hs_ext out 3 out 2 out 1 rel 2 rel 1 v 2_2 v 2_1 res stby sel go stby trig group hs control ls output, v 2 and mode control table 79. control register 1, bits bit name comment 15 ouths select mode of ouths 14 ouths_ext ouths_2 ouths_1 mode 0 0 0 hs off active and standby mode 0 0 1 hs cyclic on with timer 1 0 1 0 hs controlled by pwm4 0 1 1 hs cyclic on with timer 2 110pwm3 1x1hs on 13 out4 select mode of out4 12 out4_2 out4_1 mode 00hs off active and standby mode 01hs on 10 hs controlled by pwm4 11 hs cyclic on with timer 2 11 ouths_ext extended function of ouths; see table ouths
L99PM62GXP st spi doc id 17639 rev 4 83/102 10 out3 select mode of out3 out3 mode 0select fso active and standby mode 1select pwm3 9 out2 select mode of out2 out2 mode 0select pwm2 active and standby mode 1select timer2 8 out1 select mode of out1 out1 mode 0select pwm1 active and standby mode 1select timer1 7 rel2 select mode of rel2 rel2 mode 0 rel2 off active and standby mode 1 rel2 on active mode 6 rel1 select mode of rel1 rel1 mode 0 rel1 off active and standby mode 1 rel1 on active mode table 79. control register 1, bits (continued) bit name comment
st spi L99PM62GXP 84/102 doc id 17639 rev 4 control register 2 5v 2 4 v 2_2 v 2_1 00v 2 off in all modes 01 v 2 on in active mode; off in v 1 /v bat standby mode 10 v 2 on in active/v 1 standby mode; off in v bat standby mode 11v 2 on in all modes 3resreserved 2 stby_sel select standby mode 0v bat standby mode 1v 1 standby mode 1 go_stby execute standby mode 0 no action 1 execute standby mode 0 trig trigger bit for watchdog table 79. control register 1, bits (continued) bit name comment table 80. control register 2: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 000010 data, 8bit data, 8 bit table 81. control register 2, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 000000 000 111 function res res wu3 filt_msb wu3 filt_lsb wu2 filt_msb wu2 filt_lsb wu1 filt_msb wu1 filt_lsb res wu3 pu/pd wu2 pu/pd wu1 pu/pd res wu3 en wu2 en wu1 en group wakeup control wakeup control
L99PM62GXP st spi doc id 17639 rev 4 85/102 control register 3 table 82. control register 2, bits bit name comment 15 res reserved 14 res reserved 13, 12 wu3_filt wakeup filter configuration 11, 10 wu2_filt msb lsb 9, 8 wu1_filt 0 0 static, 64 s 0 1 enabled with timer 2; 80 s blank 1 0 enabled with timer 2; 800 s blank 1 1 enabled with timer 1; 800 s blank 7resreserved 6 wu3_pu/pd pull up or pull down configuration 5 wu2_pu/pd 0 pull down 4 wu1_pu/pd 1 pull up 3resreserved 2 wu3_en enable wake up source 1 wu2_en 0 disable 0 wu1_en 1 enable table 83. control register 3: command data bytes command byte 1 st data byte 2 nd data byte read/write address x x 000011 data, 8bit data, 8 bit table 84. control register 3, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 0 0 0 0 0 0 0 0 0 1 1 0 0 function res t1 on t1 per msb t1 per lsb res t2 on t2 per msb t2 per lsb res res wd time msb wd time lsb lin wu en can wu en wake timer en wake timer select group timer settings watchdog and cyclic wake up settings
st spi L99PM62GXP 86/102 doc id 17639 rev 4 table 85. control register 3, bits bit name comment 15 res reserved 14 t1_on timer 1 ?on? time selections 010ms 120ms 13 t1_per_msb timer 1 period selection 12 t1_per_lsb msb lsb 00 1s 01 2s 10 3s 11 4s timer 1 is restarted with a valid write command to control register 3 11 res 10 t2_on timer 2 ?on? time selection 00.1ms 11ms 9 t2_per_msb timer 2 period selection 8 t2_per_lsb msb lsb 0010ms 0120ms 1050ms 11200ms timer 2 is restarted with a valid write command to control register 3 7 res reserved 6 res reserved
L99PM62GXP st spi doc id 17639 rev 4 87/102 control register 4 5 wd_time_msb trigger window selection 4 wd_time_lsb msb lsb 0010ms 0150ms 10100ms 11200ms 3 lin_wu_en enable lin as wake up source 0disabled 1 enabled 2 can_wu_en enable can as wake up source 0disabled 1 enabled 1 wake_timer_en enable wake up by timer from v 1 standby mode (interrupt) or v bat standby mode (nreset) 0disabled 1 enabled 0 wake_timer_select timer selection for timer interrupt / wake-up of c by timer 0timer 2 1timer 1 table 85. control register 3, bits (continued) bit name comment table 86. control register 4: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 000100 data, 8bit data, 8 bit
st spi L99PM62GXP 88/102 doc id 17639 rev 4 table 87. control register 4, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 0 0 1 0 1 0 0 1 1 1 1 0 1 1 0 function res i cmp ouths rec en vlock out_en res ls ov/uv shut down_en v 1 reset lev_2 v 1 reset lev_1 lin pu en res lin txd tout en can act can loop en can patt. wake en can split on can rec only group control (other) transceiver settings table 88. control register 4, bits bit name comment 15 res reserved; must be set to zero 14 i cmp v 1 load current supervision 0 enabled; watchdog is disabled in v 1 standby when the v 1loadcurrent < i cmpthreshold 1 disabled; watchdog is automatically disabled when v 1 standby is entered 13 ouths_rec_en overcurrent auto recovery mode for ouths 0disabled 1 enabled 12 vlock_out_en voltage lock out: ov/uv status 0 over/under voltage status recovers automatically when condition disappears 1 over/under voltage status is latched until a read and clear command is performed 11 res reserved 10 ls_ov/uv shut_down_en shutdown of low-side drivers in case of over-/under voltage 0 no shutdown of low-sides in case of over/under voltage 1 shutdown low-sides in case of over/under voltage
L99PM62GXP st spi doc id 17639 rev 4 89/102 9 v1reset_level_1 select reset level 8 v1reset_level_2 v1rstlev_2 v1rstlev_1 v1 reset level 004.6v 014.35v 104.1v 113.8v 7 lin_pu_en enable internal lin pull up 0 no lin master pull-up 1 lin master pull-up 6 res must be written to ?1? 5 lin_txd_tout_en enable / disable monitoring via txd 0 no txd monitoring 1 txd monitoring; lin transmitter is switched off if txdl is dominant for t > 12 ms 4 can_act activate can transceiver 0 can transceiver deactivated active mode 1 can transceiver activated 3 can_loop_en enable looping of cantx to canrxd 0 no looping 1 txdc is looped to rxdc 2 can_patt_wake_en enable pattern wake up for can 0 no pattern wake up 1 pattern wake up 1 can_split_on enable split termination for can 0 split termination disabled active mode 1 split termination enabled table 88. control register 4, bits (continued) bit name comment
st spi L99PM62GXP 90/102 doc id 17639 rev 4 control register 5 0 can_rec_only enable can receive only mode 0 can in transceiver mode active mode 1 can in receive only mode table 88. control register 4, bits (continued) bit name comment table 89. control register 5: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 000101 data, 8bit data, 8 bit table 90. control register 5, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 111111100000000 function res pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm2 off- dc pwm freq pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc pwm1 on-dc group pwm2 setting pwm1 setting table 91. control register 5, bits bit name comment 15 res reserved; must be set to zero 14 pwm2_ off_dc_6 13 pwm2_ off_dc_5 pwm2 off_ dc_6 pwm2 off_ dc_5 pwm2 off_ dc_4 pwm2 off_ dc_3 pwm2 off_ dc_2 pwm2 off_ dc_1 pwm2 off_ dc_0 pwm duty cycle 12 pwm2_ off_dc_4 11111110%, hs off 11 pwm2_ off_dc_3 ... 10 pwm2_ off_dc_2 000001098.5% 9 pwm2_ off_dc_1 000000199.25% 8 pwm2_ off_dc_0 0000000100% hs on
L99PM62GXP st spi doc id 17639 rev 4 91/102 control register 6 7 pwm_ freq select pwm frequency 0128hz 1256hz 6 pwm1_ on_dc_6 5 pwm1_ on_dc_5 pwm1 on_ dc_6 pwm1 on_ dc_5 pwm1 on_ dc_4 pwm1 on_ dc_3 pwm1 on_ dc_2 pwm1 on_ dc_1 pwm1 on_ dc_0 pwm duty cycle 4 pwm1_ on_dc_4 1111111100%, hs on 3 pwm1_ on_dc_3 ... 2 pwm1_ on_dc_2 00000101.5% 1 pwm1_ on_dc_1 00000010.75% 0 pwm1_ on_dc_0 00000000% hs off table 91. control register 5, bits (continued) bit name comment table 92. control register 6: command and data bytes command byte 1 st data byte 2 nd data byte read/write address xx000110 data, 8bit data, 8 bit table 93. control register 6, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 1111111 000 0 000 function res pwm4 off_ dc_6 pwm4 off_ dc_5 pwm4 off_ dc_4 pwm4 off_ dc_3 pwm4 off_ dc_2 pwm4 off_ dc_1 pwm4 off_ dc_0 res pwm3 on_ dc_6 pwm3 on_ dc_5 pwm3 on_ dc_4 pwm3 on-dc_3 pwm3 on_ dc_2 pwm3 on_ dc_1 pwm3 on_ dc_0 group pwm4 setting pwm3 setting
st spi L99PM62GXP 92/102 doc id 17639 rev 4 table 94. control register 6, bits bit name comment 15 res reserved; must be set to zero 14 pwm4_ off_dc_6 13 pwm4_ off_dc_5 pwm4 off_ dc_6 pwm4 off_ dc_5 pwm4 off_ dc_4 pwm4 off_ dc_3 pwm4 off_ dc_2 pwm4 off_ dc_1 pwm4 off_ dc_0 pwm4 duty cycle 12 pwm4_ off_dc_4 11111110%, hs off 11 pwm4_ off_dc_3 ... 10 pwm4_ off_dc_2 000001098.5% 9 pwm4_ off_dc_1 000000199.25% 8 pwm4_ off_dc_0 0000000100% hs on 7 res reserved; must be set to zero 6 pwm3_ on_dc_6 5 pwm3_ on_dc_5 pwm3 on_ dc_6 pwm3 on_ dc_5 pwm3 on_ dc_4 pwm3 on_ dc_3 pwm3 on_ dc_2 pwm3 on_ dc_1 pwm3 on_ dc_0 pwm3 duty cycle 4 pwm3_ on_dc_4 1111111100%, hs on 3 pwm3_ on_dc_3 ... 2 pwm3_ on_dc_2 00000101.5% 1 pwm3_ on_dc_1 00000010.75% 0 pwm3_ on_dc_0 00000000% hs off
L99PM62GXP st spi doc id 17639 rev 4 93/102 6.2.3 status registers table 95. overview of status register data bytes 1 st data byte <15:8> 2 nd data byte <7:0> status register 1, data <15:0> function ol hs ol out4 ol out3 ol out2 ol out1 uv v 2 fail v 2 short ov oc hs oc out4 oc out3 oc out2 oc out1 oc rel2 oc rel1 group diagnosis 1 diagnosis 2 status register 2, data <15:0> function wu3 state wu2 state wu1 state wu3 wake wu2 wake wu1 wake wake can wake lin wake timer int lin perm. dom. lin txd perm dom. lin perm. rec. can rxd perm rec. can perm. rec. can perm. dom. can txd perm dom group diagnosis 3 diagnosis 4 status register 3, data <15:0> function tsd1 tw device state device state v 1 fail v 1 restart v 1 restart v 1 restart wd fail wd fail wd fail wd fail forced sleep wd forced sleep tsd2 shtv1 wd timer state wd timer state group diagnosis 5 diagnosis 6 table 96. global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value global error flag (1) communication error (2) not (chip reset or comm. error) i.e. cold start (3) tsd2 (4) tsd1 v 1 fail vs fail (5) (ov/uv) fail safe (6) active high/low high high low high high high high high default value in normal mode - after correct wd trigger or after read & clear on error flags 0010000020 power on 1000000080 power on weak battery (7) 1000001082 communication error 11000000c0 vs over or under-voltage 10100010a2 wd failure 10100001a1
st spi L99PM62GXP 94/102 doc id 17639 rev 4 status register 1 spi error (di stuck) 10100001a1 tsd1 10101000a8 tsd2 10111001b9 v 1 fail 10100100a4 other device failure (8) 10100000a0 1. the following status bits are reported in the global error flag: global status register: bits 0 - 6 status register 1: bits 0 ? 10 status register 3: bits 2, 3, 15 2. invalid clock count. 3. cleared with clr command on sr3. 4. cleared with ?read and clear? on sr3 (-> tsd1). 5. diagnosis bit only, vs fail is not a fail-safe event; cleared by read&clear. bit is automatically cleared at (vs > vsuv) and. (vs < vsov) if vlock_out_en = 0. 6. cleared with a valid wd trigger (wd fail) or by clear ing the corresponding status register related to failure. 7. slow vs ramp-up (vs undervoltage is filtered with 64 s after power-on reset). 8. the global error flag is raised due to a failure condition which is not reported in the global status register. the failure i s reported in the status registers 1 ? 3. table 96. global status register (continued) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value global error flag (1) communication error (2) not (chip reset or comm. error) i.e. cold start (3) tsd2 (4) tsd1 v 1 fail vs fail (5) (ov/uv) fail safe (6) table 97. status register 1: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit<7:0> x x 010001 data, 8bit data, 8 bit table 98. status register 1, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function ol hs ol out4 ol out3 ol out2 ol out1 uv v 2 fail v 2 short ov oc hs oc out4 oc out3 oc out2 oc out1 oc rel2 oc rel1 group diagnosis 1 diagnosis 2
L99PM62GXP st spi doc id 17639 rev 4 95/102 table 99. status register 1, bits bit name comment information storage 15 ol_hs open-load event occurred since last read out bit is latched until a ?read and clear? access 14 ol_out4 13 ol_out3 12 ol_out2 11 ol_out1 10 uv under voltage event on v s occurred since last read out vlockouten (cr4) information storage 0 automatically reset when uv condition disappears 1 bit is latched until a ?read and clear? access 9v 2 _fail v 2 fail (v 2 < 2 v for t> 2 s) event occurred since last readout bit is latched until a ?read and clear? access 8v 2 _short v 2 short (v 2 < 2 v for t > 4ms during start up) event occurred since last readout bit is latched until a ?read and clear? access 7ov over voltage event on v s occurred since last read out vlockouten (cr4) information storage 0 automatically reset when ov condition disappears 1 bit is latched until a ?read and clear? access 6 oc_hs over current event occurred since last read out bit is latched until a ?read and clear? access 5oc_out4 4oc_out3 3oc_out2 2oc_out1 1 oc_rel2 0 oc_rel1
st spi L99PM62GXP 96/102 doc id 17639 rev 4 status register 2 table 100. status register 2: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit<7:0> x x 010010 data, 8bit data, 8 bit table 101. status register 2, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function wu3 state wu2 state wu1 state wu3 wake wu2 wake wu1 wake wake can wake lin wake timer int lin perm. dom. lin txd perm dom. lin perm. rec. can rxd perm rec. can perm. rec. can perm. dom. can txd perm dom group diagnosis 3 diagnosis 4 table 102. status register 2, bits bit name comment information storage 15 wu3_state state of wux input; ?live bits? not clearable 14 wu2_state 13 wu1_state 12 wu3_wake shows wake up source (?1? = wake-up) bits are latched until a ?read and clear? access 11 wu2_wake 10 wu1_wake 9 wake_can 8 wake_lin 7 wake_timer_int 6 lin_perm_dom lin bus is dominant for t > 12 ms 5 lin_txd_perm_dom txdl pin is dominant for t > 12 ms; transmitter is disabled 4 lin_perm_rec lin bus does not follow txdl within 40 s; transmitter is disabled 3 can_rxd_perm_rec rxdc has not followed txdc for 4 times; transmitter is disabled 2 can_perm_rec can has not followed txdc for 4 times; transmitter is disabled 1 can_perm_dom can bus is dominant for t > 700 s 0 can_txd_perm_dom txdc pin is dominant for t > 700 s; transmitter is disabled
L99PM62GXP st spi doc id 17639 rev 4 97/102 status register 3 table 103. status register 3: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit<7:0> x x 010011 data, 8bit data, 8 bit table 104. status register 3, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function tsd1 tw device state_2 device state_1 v 1 fail v 1 restart_2 v 1 restart_1 v 1 restart_0 wd fail_3 wd fail_2 wd fail_1 wd fail_0 forced sleep wd forced sleep tsd2 shtv1 wd timer state_1 wd timer state_0 group diagnosis 5 diagnosis 6 table 105. status register 3, bits bit name comment information storage 15 tsd1 thermal warning / shutdown1 occurred since last readout bit is latched until a ?read and clear access? 14 tw 13 device_state state from which the device woke up bit is latched until a ?read and clear access? after a ?read and clear access?, the device state is updated after a wake up, device state is 01: v 1 standby or 10: v bat standby 12 device state_2 device state_1 state from which the device woke up 00active 01v 1 standby 10v bat standby 11flash 11 v 1 _fail v 1 fail (v 1 < 2 v for t > 2 s) event occurred since last read out bit is latched until a ?read and clear access? 10 v 1 _restart_2 number of tsd2 events which caused a restart of v 1 regulator (7 tsd2 events forces the device into v bat standby) bits are not clearable; is cleared automatically if no additional tsd2 event occurs within 1 min. 9v 1 _restart_1 8v 1 _restart_0 7wd_fail_3 number of missing watchdog triggers (15 missing watchdog trigger forces the device into v bat standby) bits are not clearable; is cleared with a proper watchdog trigger 6wd_fail_2 5wd_fail_1 4wd_fail_0
st spi L99PM62GXP 98/102 doc id 17639 rev 4 3 forced_sleep_wd device was forced to v bat standby mode because of multiple watchdog errors bits are latched until a read and clear access 2 forced_sleep_tsd 2_shtv 1 device was forced to v bat standby or multiple thermal shutdown events or a short on v 1 during startup. 1 wd_timer_state_1 status of watchdog counter of selected watchdog timing bits are not clearable 0wd_timer_state_0 wd_timer_state_1 wd_t imer_state_0 counter 0 0 0 ? 33% 0 1 33 ? 66% 1 1 66 ? 100% table 105. status register 3, bits (continued) bit name comment information storage
L99PM62GXP package and packing information doc id 17639 rev 4 99/102 7 package and packing information 7.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.2 powersso-36 package information figure 41. powersso-36 package dimensions a g00066v1
package and packing information L99PM62GXP 100/102 doc id 17639 rev 4 table 106. powersso-36 mechanical data symbol millimeters min. typ. max. a- -2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 d 10.10 - 10.50 e 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n - - 10 deg o-1.2- q-0.8- s-2.9- t-3.65- u-1.0- x 4.1 - 4.7 y 6.5 - 7.1
L99PM62GXP revision history doc id 17639 rev 4 101/102 8 revision history table 107. document revision history date revision change 24-jan-2011 1 initial release. 23-feb-2011 2 table 11: temperature warning and thermal shutdown : ?t sd2 off : updated minimum and typical values 01-jun-2011 3 updated following figures: ? figure 3: voltage source with external pnp ? figure 5: voltage source with external npn 19-sep-2013 4 updated disclaimer.
L99PM62GXP 102/102 doc id 17639 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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